In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

A method for computational storage may include storing, at a storage device, two or more portions of data, wherein a first one of the two or more portions of data comprises a first fragment of a record and a second one of the two or more portions of data comprises a second fragment of the record, and performing, by the storage device, an operation on the first and second fragments of the record. The method may further include performing, by the storage node, a second operation on first and second fragments of a second record. The operation may include a data selection operation, and the method may further include sending a result of the data selection operation to a server. The method may further include sending a result of a first data selection operation to a server.

The present invention discloses a method for external devices accessing computer memory, which includes: the external device applying to a computer for a memory space with a certain size, and receiving multiple memory blocks fed back by the computer; the external device establishing a memory mapping relation between the external device and the computer by means of a sequential storage structure or a chain storage structure; and when initiating a read-and-write operation, the external device finding the corresponding offset address in said computer according to the memory mapping relation between the external device and the computer, generating a read-and-write burst command, and actualizing read-and-write operations in the computer memory. The present invention can achieve the rapid and continuous access to multiple discontinuous memory areas of the computer memory, and improve the speed in the computer’s operating system and external devices accessing the memory.

A method of circuit conception of a computational memory circuit including a memory having memory cells, the method including: receiving an indication of the memory storage size and an indication of an instruction frequency of the instructions to be executed by the computational memory circuit; evaluating for a plurality of candidate types of memory cells, a number representing an average number of cycles of the memory of the computational memory circuit per instruction to be executed; determining, for each of the plurality of candidate types of memory cells, a minimum operating frequency of the computational memory circuit based on the number N and on the memory storage size; selecting one of the plurality of candidate types of memory cells based on the determined minimum operating frequency; and performing the circuit conception based on the selected type of candidate memory cell.

A memory device can sense stored data during memory read operations using a reference trim, and a memory built-in self-test system can perform a multiple step process to set the reference trim for the memory device. The memory built-in self-test system can set a reference trim range that corresponds to a range of available reference trim values and then select one of the reference trim values in the reference trim range as the reference trim for the memory device. The memory built-in self-test system can set the reference trim range by prompting performance of the memory read operations using different positions of the reference trim range relative to read characteristics of the memory device and set a position for the reference trim range relative to the read characteristics of the memory device based on failures of the memory device to correctly sense the stored data during the memory read operations.

Method and system for training a machine learning model based on a training dataset formed by data objects distributed across a virtual object storage service. The method comprises fetching from the virtual object storage service, the training dataset; copying the fetched training dataset on a first local storage device and maintaining a list of modifications executed on the training dataset that occurred on the virtual object storage service. The method comprises, upon receiving a request to initiate training of the machine learning model, generating a synchronized training dataset mirroring the training dataset stored in the virtual object storage service; storing the synchronized training dataset in a second local storage device; and fetching training data from the synchronized training dataset stored in the second local storage device as the training of the machine learning model is executed.

A method of storing data, a method of reading data, a device, and a storage medium are provided, which relate to a field of artificial intelligence, in particular to the fields of cloud computing technology and distributed storage technology. A specific implementation scheme includes: storing at least one target data into a target file in a storage class memory device; recording a storage address of the at least one target data in the storage class memory device in a dynamic random access memory as a first index data; and synchronously storing the first index data into the storage class memory device as a second index data.

An apparatus comprising an input to couple to a negative voltage source; and circuitry to detect whether the input has crossed a negative voltage threshold, wherein the circuitry comprises a first capacitor that is selectively coupled to the first input and a second capacitor that is selectively coupled to a second input coupled to a positive voltage source.

A method for memory access may include receiving, at a device, a first memory access request for a parallel workload, receiving, at the device, a second memory access request for the parallel workload, processing, by a first logical device of the device, the first memory access request, and processing, by a second logical device of the device, the second memory access request. Processing the first memory access request and processing the second memory access request may include parallel processing the first and second memory access requests. The first logical device may include one or more first resources. The method may further include configuring the first logical device based on one or more first parameters of the parallel workload. The method may further include allocating one or more first resources to the first logical device based on at least one of the one or more first parameters of the parallel workload.

A vehicle memory sub-system can be switched from a normal mode to a pre-shutdown mode and initiate a media management operation before shutting down. The mode switch and/or media management operation can be performed in response to receiving a shutdown or pre-shutdown command for the vehicle. After completion of the memory management operation the vehicle and/or memory sub-system can be shutdown.