A current loop includes a receiver assembly and a transmitter assembly. The current loop also includes: a first conductor between the receiver assembly and the transmitter assembly; and a second conductor between the receiver assembly and the transmitter assembly to complete the current loop. The transmitter assembly includes: a Highway Addressable Remote Transducer (HART) modem; a component in communication with the HART modem via a partial set of Universal Asynchronous Receiver-Transmitter (UART) communication lines; and a break extension protocol controller coupled to or included with the HART modem and configured to support UART and non-UART communications between the HART modem and the component using the partial set of UART communication lines.

Disclosed is a fieldbus transmitter interface for a field device or a control center. The fieldbus transmitter interface comprises a computing unit, a digital gate, an analog transmission filter and a transmitter interface output. The computing unit is connected to the digital gate, and the digital gate is connected to the analog transmission filter, and the analog transmission filter is connected to the transmitter interface output. The computing unit comprises a pulse width modulator and a pulse width modulator clock that is suitable for generating a secondary signal coded by a duty cycle which is varied over time by the pulse width modulator clock. The pulse width modulator superimposes the secondary signal with a carrier signal, so that a digital transmission signal with a frequency of less than 150 kHz is generated. The digital gate and the analog transmit filter convert the digital transmission signal into an analog loop signal.

A current loop includes a receiver assembly and a transmitter assembly. The current loop also includes: a first conductor between the receiver assembly and the transmitter assembly; and a second conductor between the receiver assembly and the transmitter assembly to complete the current loop. The transmitter assembly includes: a Highway Addressable Remote Transducer (HART) modem; a component in communication with the HART modem via a partial set of Universal Asynchronous Receiver-Transmitter (UART) communication lines; and a break extension protocol controller coupled to or included with the HART modem and configured to support UART and non-UART communications between the HART modem and the component using the partial set of UART communication lines.

A communicating entities include one master entity, configured for communicating according to a first protocol at least, and a plurality of slave entities. The slave entities include a first group of slave entities able to support communications according to said first protocol and unable to support communications according to a second protocol, and a second group of slave entities able to support communications according to at least said second protocol. The first protocol is implemented by a token passing with communication data from the master entity to successively each neighbour slave entity, until the token reaches again the master entity, defining thus a first cycle according to the first protocol. The second protocol is implemented by passing a data frame including data intended to entities of said second group, one current entity of said second group, when receiving said data frame.

An electronic circuit system includes a main device that generates first and second strobe signals and a clock signal, a first peripheral device that uses the first strobe signal to generate a first output signal in a first lane in response to the clock signal, and a second peripheral device that uses the second strobe signal to generate a second output signal in a second lane in response to the clock signal. The main device determines if the first peripheral device is coupled to the main device through the first lane based on the first output signal. The main device determines if the second peripheral device is coupled to the main device through the second lane based on the second output signal. The main device also has the ability to detect if a peripheral device is faulty and to select a valid configuration of peripheral devices.

Disclosed is a fieldbus transmitter interface for a field device or a control center. The fieldbus transmitter interface comprises a computing unit, a digital gate, an analog transmission filter and a transmitter interface output. The computing unit is connected to the digital gate, and the digital gate is connected to the analog transmission filter, and the analog transmission filter is connected to the transmitter interface output. The computing unit comprises a pulse width modulator and a pulse width modulator clock that is suitable for generating a secondary signal coded by a duty cycle which is varied over time by the pulse width modulator clock. The pulse width modulator superimposes the secondary signal with a carrier signal, so that a digital transmission signal with a frequency of less than 150 kHz is generated. The digital gate and the analog transmit filter convert the digital transmission signal into an analog loop signal.

An example computing system includes a baseboard management controller (BMC), a motherboard, and a daughterboard communicatively coupled to the motherboard. The BMC includes a serial interface. The daughterboard includes a universal asynchronous receiver/transmitter (UART) terminal, a bridging chip, and a microcontroller communicatively coupled to the BMC via the bridging chip. The BMC establishes a serial connection, through the serial interface and the UART terminal, with the microcontroller.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.

Disclosed is a signal processing circuit, a contactless connector, a signal processing method and a storage medium. One end of a cable of the signal processing circuit can be connected to a device and the other end of the cable of the signal processing circuit is connected to a port processing unit for receiving a signal transmitted by the device and/or transmitting a signal to the device; one end of the port processing unit is connected to the cable, and the other end of the port processing unit is connected to a signal processing unit for acquiring a data communication transmission mode of a port of the device connected to a connector, and performing interface configuration on the cable according to the data communication transmission mode; and the signal processing unit is connected to the main coil or the secondary coil, and is configured to, if receiving the signal transmitted by the device, transmit the signal to the main coil and/or the secondary coil, and/or is configured to, if receiving the signal transmitted by the main coil and/or the secondary coil, transmit the signal to the device according to the data communication transmission mode. According to the present application, the contactless connector adapts to different transmission protocols of the device port while remote wireless signal transmission is realized.

An apparatus includes a plurality of output ports and a processor. The output ports may each be configured to connect to a respective trigger device and generate an output signal to activate the respective trigger device. The processor may be configured to determine a number of the trigger devices connected to the output ports, determine a timing between each of the number of the trigger devices connected, convert the timing for each of the trigger devices to fit a standard timing using offset values specific to each of the trigger devices and perform a trigger routine to trigger the output signal for each of the trigger devices connected. The trigger routine may activate each of the trigger devices connected according to an event. The offset values may delay triggering the trigger devices to ensure that the trigger devices are sequentially activated at intervals that correspond consistently with the standard timing.