A multiple processor architecture with flexible external input/output interface is provided. In one embodiment, an open flexible processor architecture avionics device comprises: a multiple processor architecture having a primary processor, a secondary processor, a random access memory (RAM) coupled to at least the secondary processor, and a shared memory coupled to the primary and secondary processor; and a flexible input/output (I/O) interface coupled to the multiple processor architecture, wherein the flexible I/O interface provides I/O access to the primary processor using a fixed I/O protocol, and provides I/O access to the secondary processor using at least one re-configurable I/O protocol; wherein the primary processor is dedicated to executing embedded software for implementing a primary base functionality, the primary processor has read and write access to the shared memory, and the primary processor is not reprogrammable; and wherein the secondary processor has read-only access to the shared memory and is programmable.

A method for stack timing adjustment for serial communications is provided. The method includes receiving a USB communication, decoding the USB communication into UART frames, and adjusting the timing of the UART frames according to a serial protocol.

A system may include a digital sensor system including a sensor element and a digital interface. The digital interface may provide a wake-up signal based on a sensing action being performed by the sensor element after a predefined event is detected by the digital sensor system. The system may include a microcontroller to receive the wake-up signal provided by the digital interface, and wake from a sleep mode based on receiving the wake-up signal provided by the digital interface.

In a data processing device including two sets of circuit pairs which are respectively duplicated in two clock domains which are asynchronous to each other, an asynchronous transfer circuit that transfers a payload signal is provided between the two sets of circuit pairs. The asynchronous transfer circuit includes two sets of a pair of bridge circuits which are respectively connected to the two sets of circuit pairs, and asynchronously transfers the payload signal and a control signal indicating a timing at which the payload signal is stable on a reception side. The two sets of a pair of bridge circuits and the payload signals can be duplicated, but the control signal is not duplicated, and the received payload signal is used for timing control to supply an expected same time difference, to the pair of duplicated circuits. This enables asynchronous transfer between circuits duplicated in the asynchronous clock domains.

A computer-implemented method manages I/O queues in a host clustered system. The method includes, receiving, from a first virtual machine (VM), a request to establish a set of I/O queues in a storage system, and the first VM is supported by a first host. The method further includes, mapping a data volume to a target storage system, wherein the data volume is related to the request. The method includes, sending a first connection request from the first host to the target storage system. The method further includes, establishing, in response to the first connection request, a connection between the first host and the target storage system. The method incudes, blocking a second connection request, wherein the second connection request is directed to a second storage system, the second storage system being included in the storage system.

A system may include a first device and a second device communicatively coupled to the first device via a communications bus, wherein the communications bus comprises a single clock line for transmission of a clock signal from the first device to the second device, a single frame line for transmission of a frame alignment signal from the first device to the second device, and at least one communications channel for serialized communication of payloads of data between the first device and the second device, wherein the payloads of data have at least two different latencies.

A module for asynchronous differential serial communication on a bus is disclosed. The module is connectable to the bus in a first connecting mode, wherein a non-inverting terminal of the module is connected to a non-inverted bus signal line and an inverting terminal is connected to an inverted bus signal line, and a second connecting mode given by an inverse of the first connecting mode. The module includes a detector determining the connecting mode based on the binary state of a start bit of a reception signal provided by a transceiver of the module based on a received communication signal and a binary state of a first bit of a reference signal corresponding to a voltage difference between the voltages of the signals received via the non-inverted and the inverted terminal during reception of this communication signal.

Methods and systems for data communication using the single wire communication protocol and the universal asynchronous receiver-transmitter (UART) communication protocol are disclosed. The method includes receiving by a first device a reset pulse. The method includes operating the first device in a standard speed single wire protocol if the width of the reset pulse is between 480 and 640 micro seconds. The method includes operating the first device in an overdrive speed single wire protocol if the width of the reset pulse is between 48 and 80 micro seconds. The method includes operating the first device in a universal asynchronous receiver-transmitter (UART) protocol if the width of the reset pulse is between 240 and 480 micro seconds. The method includes transmitting by the first device an answer responsive to the reset pulse. The method includes synchronizing the first device with a host device responsive to the reset pulse.

Sideband signaling in Universal Serial Bus (USB) Type-C communication link allows multiple protocols that are tunneled through a USB link, where sideband signals may be provided through the sideband use (SBU) pins. Further, the SBU pins may be transitioned between different modes of sideband signals. In particular, signals in an initial mode may indicate a need or desire transition to a second mode. After a negotiation, linked devices agree to transition, the two devices may transition to the second mode. By providing this inband sideband signaling that allows mode changes, more protocols can be tunneled with accompanying sideband signaling and flexibility of the USB link is expanded.

In one embodiment, an apparatus includes: a transmitter to send a first plurality of flits to a second device coupled to the apparatus via a link; and a control circuit coupled to the transmitter to change a configuration of the link from a flit-based encoding to a packet-based encoding. In response to the configuration change, the transmitter is to send a first plurality of packets to the second device via the link. Other embodiments are described and claimed.