An embedded file network server based on a seismic data stream includes a broadband power management module, a main control unit, a serial-port-to-RS232 module, a PHY bridge layer, an SD card, and a network interface. The main control unit includes serial port, an SDIO interface, an internal RAM, DMA units, and a MAC drive layer. The main control unit performs seismic data interaction with an external device through the serial port, and receives seismic data through an internal interruption, and the received seismic data stream is stored in the internal RAM. The internal RAM transfers the received seismic data stream to the SDIO interface and MAC driver layer through the DMA units. The SDIO interface stores the seismic data stream in the SD card for data backup. The MAC driver layer is coupled to the PHY bridge layer for inputting and outputting the seismic data stream.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, are described for performing asymmetric data communication at a host-device interface of a system. The methods include identifying devices coupled to a host of the system and generating a system topology that identifies a connectivity of the devices and identifies bus lanes that enable data transfers at the system. The host determines that a first connection between the host and a first device of the multiple devices has an asymmetric bandwidth requirement. The host configures a set of bus lanes of a data bus connecting the first device and the host to allocate a different number of the bus lanes to data egress from the host than to data ingress to the host. The bus lanes are configured to allocate the differing number of bus lanes based on the asymmetric bandwidth requirement of the first connection.

An embedded file network server based on a seismic data stream includes a broadband power management module, a main control unit, a serial-port-to-RS232 module, a PHY bridge layer, an SD card, and a network interface. The main control unit includes serial port, an SDIO interface, an internal RAM, DMA units, and a MAC drive layer. The main control unit performs seismic data interaction with an external device through the serial port, and receives seismic data through an internal interruption, and the received seismic data stream is stored in the internal RAM. The internal RAM transfers the received seismic data stream to the SDIO interface and MAC driver layer through the DMA units. The SDIO interface stores the seismic data stream in the SD card for data backup. The MAC driver layer is coupled to the PHY bridge layer for inputting and outputting the seismic data stream.

A serial communication apparatus capable of efficiently eliminating a timing lag between serial data transferred via a plurality of routes in serial communication is provided. The serial communication apparatus transfers serial data transmitted from a transmitting side communication unit disposed on a transmitting side to a receiving side communication unit disposed on a receiving side via a plurality of lanes. The transmitting side communication unit comprises a packet transmitting unit configured to divide transmission data into equal parts according to the number of the lanes, distribute the divided transmission data to each lane as a data main body, and add header information indicating the type of the transmission data to the divided transmission data distributed to each lane. The receiving side communication unit comprises a received packet skew adjusting unit configured to adjust skew of data received in each lane.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an asynchronous packet network; a plurality of configurable circuits arranged in an array, each configurable circuit coupled to the asynchronous packet network and adapted to perform a plurality of computations; and a dispatch interface circuit adapted to partition the plurality of configurable circuits into one or more separate partitions of configurable circuits and to load one or more computation kernels into each partition of configurable circuits. The dispatch interface circuit may load balance across the partitions of configurable circuits by starting threads for execution in the partition having the highest number of available thread identifiers. The dispatch interface may also assert a partition enable signal to merge the one or more separate partitions and assert a stop signal to all configurable circuits of the one or more separate partitions of configurable circuits.

An apparatus and method coupling a first and a second data bus comprising selectors for routing first bus egress lanes to egress memories, each egress memory coupled to one second bus egress lane, where the second bus has more egress lanes than the first. Each egress memory corresponds to one second bus egress lane. A first FSM selecting which first bus egress lane to load into each egress memory synchronous with the first bus clock. A second FSM outputting egress memory values to the second bus synchronous with the second bus clock. A set of ingress memories, each memory coupled to one second bus ingress lane and to an input of each ingress selector. A third FSM loading the ingress memories synchronous with the second bus clock. A fourth FSM selecting which ingress memory to route to each first bus ingress lane synchronous with the first bus clock.

In one embodiment, an apparatus includes: a transmitter to send a first plurality of flits to a second device coupled to the apparatus via a link; and a control circuit coupled to the transmitter to change a configuration of the link from a flit-based encoding to a packet-based encoding. In response to the configuration change, the transmitter is to send a first plurality of packets to the second device via the link. Other embodiments are described and claimed.

In one embodiment, an apparatus includes: a transmitter to send a first plurality of flits to a second device coupled to the apparatus via a link; and a control circuit coupled to the transmitter to change a configuration of the link from a flit-based encoding to a packet-based encoding. In response to the configuration change, the transmitter is to send a first plurality of packets to the second device via the link. Other embodiments are described and claimed.

A sound processing method for a sound device including at least a physical controller, connectable to a sound processing apparatus, the method including, control the physical controller to operate in a first mode to execute an assignable function in the sound device, and a second mode to execute a preassigned function in the sound processing apparatus in a state where the sound device is connected thereto, detecting whether the sound device is connected to the sound processing apparatus, and receiving a switching instruction to switch from the first mode to the second mode after detecting connection between the sound device and the sound processing apparatus.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, are described for performing asymmetric data communication at a host-device interface of a system. The methods include identifying devices coupled to a host of the system and generating a system topology that identifies a connectivity of the devices and identifies bus lanes that enable data transfers at the system. The host determines that a first connection between the host and a first device of the multiple devices has an asymmetric bandwidth requirement. The host configures a set of bus lanes of a data bus connecting the first device and the host to allocate a different number of the bus lanes to data egress from the host than to data ingress to the host. The bus lanes are configured to allocate the differing number of bus lanes based on the asymmetric bandwidth requirement of the first connection.