Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, are described for performing asymmetric data communication at a host-device interface of a system. The methods include identifying devices coupled to a host of the system and generating a system topology that identifies a connectivity of the devices and identifies bus lanes that enable data transfers at the system. The host determines that a first connection between the host and a first device of the multiple devices has an asymmetric bandwidth requirement. The host configures a set of bus lanes of a data bus connecting the first device and the host to allocate a different number of the bus lanes to data egress from the host than to data ingress to the host. The bus lanes are configured to allocate the differing number of bus lanes based on the asymmetric bandwidth requirement of the first connection.

A modular interconnection system is disclosed. In some embodiments, the modular interconnection system comprising a server fabric adapter (SFA) on a primary circuit board, the SFA configured to perform peripheral component interconnect express (PCIe) interconnection or compute express link (CXL) interconnection; a plurality of ports on one or more PCIe slots configured to connect the SFA to external resources; and a PCIe slot adaptation device configured to adapt a first lane count slot of the one or more PCIe slots to support a second lane count device.

In one general aspect, a method can include configuring a first connector of a particular type included in a first multipurpose port located on a first side of a computing device to connect the computing device to a first peripheral device, transporting one or more of power, high-speed data, and display data between the computing device and the first peripheral device using the first multipurpose port, configuring a second connector of the particular type included in a second multipurpose port located on a second side of the computing device to connect the computing device to a second peripheral device, and transporting one or more of power, high-speed data, and display data between the computing device and the second peripheral device using the second multipurpose port.

A method includes receiving, by a storage driver associated with a storage controller and a corresponding storage array, a data structure associated with an I/O request from a host, wherein the data structure is indicative of a virtual address. A top layer and a RAID core layer of a RAID miniport driver execute asynchronously to perform preprocessing operations including generating a linked plurality of physical I/O (PIO) data structures in accordance with the virtual address and a RAID configuration of the storage array, and storing a pointer to the linked plurality of PIO data structures. A protocol layer of the RAID miniport driver may then be executed synchronously to transfer, in accordance with the linked plurality of PIO data structures, I/O data corresponding to the I/O request between the storage controller and the storage array. Interrupt operations may then be performed synchronously to indicate completion of the I/O request to the host.

In a data processing device including two sets of circuit pairs which are respectively duplicated in two clock domains which are asynchronous to each other, an asynchronous transfer circuit that transfers a payload signal is provided between the two sets of circuit pairs. The asynchronous transfer circuit includes two sets of a pair of bridge circuits which are respectively connected to the two sets of circuit pairs, and asynchronously transfers the payload signal and a control signal indicating a timing at which the payload signal is stable on a reception side. The two sets of a pair of bridge circuits and the payload signals can be duplicated, but the control signal is not duplicated, and the received payload signal is used for timing control to supply an expected same time difference, to the pair of duplicated circuits. This enables asynchronous transfer between circuits duplicated in the asynchronous clock domains.

An information processing device includes: an acquisition unit configured to acquire a determination result of a state of a user, who has given a transmission job execution instruction, determined based on biological information of the user; and a job control unit configured to control an execution of the transmission job according to the user state determination result, wherein when it is determined that the user is in an off-normal state, the job control unit executes a confirmation request process to request the user to make a confirmation related to the transmission job.

A routing method that may be performed by a system on chip of a backplane that is connected between a plurality of hosts and a plurality of devices. The routing method may include: monitoring traffic of the plurality of devices; determining mode types of the plurality of devices according to the monitored traffic; and performing routing to allocate lanes between the plurality of devices and the backplane according to the mode types.

A data transmission system includes a first apparatus that is connected to a first external apparatus using the first transmission scheme and a second apparatus that is connected to a second external apparatus using the first transmission scheme. The first apparatus is connected to the second apparatus using a second transmission scheme that is different from the first transmission scheme. When the operation mode of the first apparatus in the first transmission scheme and the operation mode of the second apparatus in the first transmission scheme are different, data in the first external apparatus or the second external apparatus is transmitted to the second external apparatus or the first external apparatus, respectively, via the first apparatus and the second apparatus.

Method for digital, bidirectional data transmission between a position measuring system (3-7) and a motor control device (1) and/or an evaluation unit based on the transmission of frames (34, 35, 36) of a predefined bit length in chronologically sequential time slots (28-30), wherein a primary master (1) communicates via a two wire bus line (2) with the position measuring system (3-7) and/or the motor unit (11, 14) and/or the evaluation unit with a primary slave (3) disposed there, and that additional sub-slaves (12, 15) can be coupled in parallel to the primary slave (3), which sub-slaves communicate on the same bus line (2), which the primary master (1) uses with the primary slave (3).

In a system where multiple controllers share a link interface but are not all (1) compatible with the same configuration of the physical layer or (2) using the same clocking, a configuration arbitration subsystem intercepts, organizes, and re-clocks configuration-access requests from the various controller agents. Priorities are assigned according to stored policies. The configuration arbiter grants configuration access to the top-priority agent, synchronizing the agent's message with the arbiter's clock. Lower-priority agents' messages are stored in command queues until they ascend to top priority. Besides preventing timing conflicts and streamlining the coordination of clocks, the configuration arbiter may provide access to physical-layer registers beyond the controllers' built-in capabilities to further optimize configuration.