A method for synchronizing a data signal in a bus environment is suggested, the method may include providing multiple clock phases based on a reference oscillator; determining a phase out of the multiple clock phases for a transition of a data signal; and synchronizing the data signal based on the phase determined.

Various embodiments of systems and methods to interleave high priority key-value transactions together with lower priority transactions, in which both types of transactions are communicated over a shared input-output medium. In various embodiments, a central-processing-unit (CPU) initiates high priority key-value transactions by communicating via the shared input-output medium to a key-value-store. In various embodiments, a medium controller blocks or delays lower priority transactions such that the high priority transactions may proceed without interruption. In various embodiments, both of the types of transactions are packet-based, and the system interrupts a lower priority transaction at a particular packet, then completes the high priority transaction, then completes the lower priority transaction. In various embodiments, a network-interface-card (NIC) reduces latency of key-value transactions in a distributed data store by delaying any packet or transaction that may interrupt or prevent immediate delivery of a key to a destination server holding a key value.

A technique includes holding a bus interface of a removable device that is inserted into a connector of a computer system in a state to prevent the device from communicating with a communication link. The communication link is coupled to the connector and is associated with operating system access to the device. The method includes a baseboard management controller communicating with the device using a channel other than the communication link while the bus interface of the device is held in the state; the baseboard management controller performing a security operation corresponding to the device based on the communication with the device using the channel; and the baseboard management controller releasing the bus interface of the device from the state to allow the device to communicate with the communication link in response to the baseboard management controller completing the security operation.

Embodiments herein describe techniques for separating data transmitted between I/O functions in an integrated component and a host into separate data paths. In one embodiment, data packets are transmitted using a direct data path that bypasses a switch in the integrated component. In contrast, configuration packets (e.g., hot-swap, hot-add, hot-remove data, some types of descriptors, etc.) are transmitted to the switch which then forwards the configuration packets to their destination. The direct path for the data packets does not rely on switch connectivity (and its accompanying latency) to transport bandwidth sensitive traffic between the host and the I/O functions, and instead avoids (e.g., bypasses) the bandwidth, resource, store/forward, and latency properties of the switch. Meanwhile, the software compatibility attributes, such as hot plug attributes (which are not latency or bandwidth sensitive), continue to be supported by using the switch to provide a configuration data path.

A method for managing communications involving a lockstep processing comprising at least a first processor and a second processor can include receiving, at a data synchronizer, a first signal from a first device. The method can also include receiving, at the data synchronizer, a second signal from a second device. In addition, the method can include determining, by the data synchronizer, whether the first signal is equal to the second signal. When the first signal is equal to the second signal, the method can include transmitting, by the data synchronizer, the first signal to the first processor and the second signal to the second processor. Specifically, in example embodiments, transmitting the first signal to the first processor can occur synchronously with transmitting the second signal to the second processor.

A memory system comprises a memory and a physical layer circuit. The memory system comprises a memory, a data bus and a single-pin STB. The memory receives a parallel command though the data bus, and receives a serial command through the STB. The physical layer circuit is configured to transmit the parallel command to the data bus. The physical layer circuit is configured to convert STB input data from the controller into the serial command and transmit the serial command to the STB.

An electronic device includes: a first input node configured to receive a dock signal; a second input node configured to receive an activation signal or a deactivation signal; a filter circuit responsive to: (a) the activation signal to activate the filter circuit to block the dock signal; or (b) the deactivation signal to deactivate the filter circuit to pass the dock signal; and an output node configured for coupling to a synchronous I/O interface of an integrated circuit to control operation of the synchronous I/O interface.

Provided herein are systems and methods for performing dynamic adaption and correction for internal delays in devices connected to a common time-multiplexed bus. The methods allow devices to operate reliably at a higher bus frequency by correcting for inherent and unknown delays within the components and in the system by measuring the actual delays using multiple readings with the bus. Intrinsic noise and jitter are used to increase the precision of the measurements, thereby essentially using these uncertainties as self-dithering for increased measurement resolution. During adaption, delays may be adjusted in multiple step sizes to speed adaption time.

This application provides a data processing method, an apparatus, and a system. In an example, a peripheral device interconnect express (PCIe) device establishes a first PCIe link to a host through a first interface and a second PCIe link to the host through a second interface. The host sends first data to the PCIe device through the first PCIe link and sends second data to the PCIe device through the second PCIe link, wherein both the first PCIe link and the second PCIe link are in an active state during data transmission.

A processing system includes a communication system and a processing core configured to generate write requests. A circuit has associated a slave interface circuit configured to manage an address sub-range and selectively forward write requests addressed to a given address. Configuration data specifies whether the given address is protected/unprotected and locked/unlocked. In response to a received write request, address and data are extracted and a determination based on the configuration data is made as to whether the extracted address is protected/unprotected, and locked/unlocked. When the extracted address is unprotected or unlocked, the slave interface forwards the write request. When the extracted address is protected and locked, the slave interface generates an unlock signal in response to a comparison of the extracted address with the extracted data, with the unlock signal being asserted when the extracted data satisfy a predetermined rule with respect to the extracted address.