Methods, systems, and devices for memory operations that support configuring a channel, such as a command/address (C/A) channel, are described. A configuration of a C/A channel may be dynamically adapted based on power saving considerations, control information execution latency, or both. Configuring a C/A channel may include determining a quantity of pins, or a quantity of cycles, both for communicating control information over the C/A channel. The quantity of pins may be determined based on previous control information transmissions, characteristics of a memory device, or predicted control information transmissions, or any combination thereof in some cases. The determined quantity of pins, quantity of cycles, or both may be explicitly or implicitly indicated to other devices (e.g., that use the C/A channel).

A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks.

The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

The present invention provides a method performed by a secure digital (SD) card supporting both an SD mode and a peripheral component interconnect express (PCIe) mode for initializing the SD card. The method includes: (a) after receiving a first supply voltage through a first voltage supply pin from a host coupled to the SD card, entering the SD mode if the SD card is not in the PCIe mode and a CMD0 command for entering the SD mode is received through a command pin from the host coupled to the SD card; and (b) after receiving the first supply voltage through the first voltage supply pin from the host coupled to the SD card, performing a PCIe linkup process if the SD card is not in the SD mode and a second supply voltage is received through a second voltage supply pin from the host coupled to the SD card. The SD card enters the PCIe mode if the PCIe linkup process succeeds.

In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.

A method may include receiving, at a storage device, a command for a data transfer between the storage device and a host, determining a specified data rate for the data transfer, and performing the data transfer between the storage device and the host based on the command, wherein the storage device may control the data transfer based on the specified data rate. The data transfer may include a peak portion and an idle portion. The method may further include controlling, at the storage device, a peak portion and an idle portion of the data transfer based on the specified data rate. The method may further include controlling, at the storage device, the data transfer based on a peak burst size. The specified data rate may be received from the host and/or determined by the storage device by monitoring one or more parameters of a data transfer.

An integrated circuit device outputs a sequence of differently delayed calibration data timing signals to a DRAM component via a data-signal timing line as part of a timing calibration operation and then stores a delay value, based on at least one of the calibration data timing signals, that compensates for a difference in signal propagation times over the data-signal timing line and a command/address-signal timing line. After the timing calibration operation, the integrated circuit device outputs write data to the DRAM component and outputs a write data timing signal, delayed according to the delay value, to via the data-signal timing line to time reception of the first write data within the DRAM.

Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.