The present invention reliably and sufficiently corrects a voltage variation in data signal lines in a display device resulting when sampling analog video signals, while suppressing increase in layout area. In a data signal line drive circuit of an active matrix liquid crystal display device, a video signal Svi is sampled by an Nch transistor (SWk) which has a parasitic capacitance (Cgd) that causes a voltage drop in a data signal line SL3(i−1)+k (i=1 through n; k=1, 2, 3). To correct this, an inversion delayer (342) makes logical inversion of the transistor (SWk)'s control signal Sck and delays the inverted signal for a predetermined time to generate an inversion delayed signal Srdk, and applies this inversion delayed signal Srd to the data signal line 3(i−1)+k via a correction capacitance element (Cc). The inversion delayer (342) makes the inversion delayed signal Srdk start its change from an L level voltage to a H level voltage after the Nch transistor (SWk) has assumed an OFF state.

A thin-film transistor (TFT) array substrate is provided. The TFT array substrate is structured to change the way that sub-pixels are arranged so that during a displaying period of a frame of image, the sub-pixels that have inconsistent brightness/darkness become alternate with each other spatially so that a displaying defect of vertical bright/dark lines can be improved and the overall resistance of the data line can be reduced to thereby reduce resistance-capacitance delay and prevent incorrect charging at a tail end of a scan line or a data line.

The resolution of a low-resolution image is made high and a stereoscopic image is displayed. Resolution is made high by super-resolution processing. In this case, the super-resolution processing is performed after edge enhancement processing is performed. Accordingly, a stereoscopic image with high resolution and high quality can be displayed. Alternatively, after image analysis processing is performed, edge enhancement processing and super-resolution processing are concurrently performed. Accordingly, processing time can be shortened.

An object of the present invention is to decrease the resistance of a power supply line, to suppress a voltage drop in the power supply line, and to prevent defective display. A connection terminal portion includes a plurality of connection terminals. The plurality of connection terminals is provided with a plurality of connection pads which is part of the connection terminal. The plurality of connection pads includes a first connection pad and a second connection pad having a line width different from that of the first connection pad. Pitches between the plurality of connection pads are equal to each other.

A display driver includes a line latch circuit; a first D/A conversion circuit; a second D/A conversion circuit; a first amplifier circuit configured to initialize charges of a capacitor of a first switched capacitor circuit in a first initialization period and output a data voltage in a first output period; a second amplifier circuit configured to initialize charges of a capacitor of a second switched capacitor circuit in a second initialization period and output a data voltage in a second output period; and a control circuit. The control circuit is configured to end the second initialization period of the second amplifier circuit before display data is latched by the line latch circuit at a latch timing and an output of the first amplifier circuit changes.

In a first output mode, a signal in which a data pulse having a positive polarity voltage value appears in a predetermined cycle is output as a positive polarity gradation data signal, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with a phase different from the positive polarity gradation data signal is output as a negative polarity gradation data signal. In a second output mode, the above positive polarity gradation data signal is generated, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with the same phase as the positive polarity gradation data signal is output as the negative polarity gradation data signal. The first and second output modes are alternatively executed, and the output mode is switched within a predetermined period at intervals of the predetermined period.

The disclosure provides a voltage adjustment method and a voltage adjustment device for a display panel, and a display device. The method includes: detecting whether an absolute value of a difference between a first gray scale data of a first sub pixel and a second gray scale data of a second sub pixel in a static picture area is larger than a preset gray scale threshold; if so, acquiring the first gray scale data; and inputting a target data voltage to the data line according to the first gray scale data, to adjust an original pixel voltage to the first sub pixel into a target pixel voltage and to cause an absolute value of a difference between a first voltage difference in the positive frame and a second voltage difference in the negative frame to be smaller than a preset voltage difference threshold.

The invention relates to a source driver and a composite level shifter. The source driver comprises a data buffer circuit, a plurality of level shifters and a plurality of driving circuits. The data buffer circuit receives and registers a plurality of pixel data during a driving period. The level shifters convert the voltage levels of the pixel data registered in the data buffer circuit during the driving period. The driving circuits generate a plurality of source signals according to the converted pixel data during driving period. The data buffer circuit may comprise a plurality of composite level shifters for converting the voltage levels of the pixel data, and latching the converted pixel data.

A method for compensating for a difference between positive and negative polarities of a display panel is provided. The display panel is electrically connected to a source driver, and the source driver includes first and second output drivers alternately connected to a same data line in the display panel. The method may include: detecting positive and negative polarity effective voltages of the display panel; adjusting a driver setting of at least one of the first and second output drivers based on the positive and negative polarity effective voltages, to change magnitudes of the positive and/or negative polarity effective voltages; and when the positive and negative polarity effective voltages relative to a common mode voltage are same in absolute value, obtaining an adjusted driver setting and applying the adjusted driver setting to the at least one of the first and second output drivers.

A display device includes: a first pixel including a first sub-pixel, a second sub-pixel, and a third sub-pixel; and a second pixel including the first sub-pixel, the second sub-pixel, and a fourth sub-pixel. The first pixel and the second pixel are alternately arranged in a row direction and a column direction. The third sub-pixel and the fourth sub-pixel are alternately arranged in the column direction. A branch electrode in one of two first sub-pixels adjacent in the column direction extends in a first direction, and a branch electrode in the other thereof extends in a second direction. A branch electrode in one of two second sub-pixels adjacent in the column direction extends in the first direction, and a branch electrode in the other thereof extends in the second direction. Each branch electrode in the third sub-pixel and the fourth sub-pixel includes a bending portion.