The Non-Volatile Arithmetic Memory Operators (NV-AMO) consisting of non-volatile memory devices for storing non-volatile data are applied to perform the arithmetic operations over volatile variable data and the non-volatile data. The NV-AMO can save arithmetic computation power by reducing the data amount fetching from the memory units. The NV-AMO can also be configured multiple-times for new computations. The constructions of NV-AMO in Arithmetic Logic Units (ALU) can be applied in DSP (Digital Signal Processor) computations and DNN (Deep Neural Network) computations.

A sensing circuit of nonvolatile memory device includes a precharge current generator, an adjusting transistor, and an adaptive control voltage generator. The precharge current generator connected to a sensing node and generates a precharge current provided to a bit-line of the nonvolatile memory device, in response to a precharge signal. The adjusting transistor, connected between the sensing node and a first node, adjusts an amount of the precharge current provided to the bit-line in response to a first control voltage. The adaptive control voltage generator generates a control current proportional to an operating temperature, in response to the precharge signal and a second control voltage and boosts a level of the first control voltage in proportion to the operating temperature. The second control voltage is inversely proportional to the operating temperature.

Certain aspects of the present disclosure are generally directed to non-volatile memory (NVM) and techniques for operating and fabricating NVM. Certain aspects provide a memory cell for implementing NVM. The memory cell generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the second semiconductor region being disposed between and having a different doping type than the first and third semiconductor regions. The memory cell also includes a fourth semiconductor region disposed adjacent to and having the same doping type as the third semiconductor region, a first front gate region disposed adjacent to the second semiconductor region, and a first floating front gate region disposed adjacent to the third semiconductor region. In certain aspects, the memory cell includes a back gate region, wherein the second semiconductor region is between the first front gate region and at least a portion of the back gate region.

A shared floating gate device, the device including an nFET, a pFET including a different material than that of the nFET, and a floating gate.

A semiconductor device includes a memory cell formed on a semiconductor substrate. The memory cell includes a first source region and a first drain region that are formed in the semiconductor substrate and a first selection gate, and a first floating gate disposed in series between the first source region and the first drain region. A first floating gate transistor including the first drain region and the first floating gate has a threshold set lower than a threshold of a first selection gate transistor including the first source region and the first selection gate.

Techniques are provided for pre-charging NAND strings during a programming operation. The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge phase of a programming operation, an overdrive voltage is applied to some memory cells and a bypass voltage is applied to other memory cells. The overdrive voltage allows the channel of an unselected NAND string to adequately charge during the pre-charge phase. Adequate charging of the channel helps the channel voltage to boost to a sufficient level to inhibit programming of an unselected memory cell during a program phase. Thus, program disturb is prevented, or at least reduced. The technique allows, for example, programming of memory cells in a middle vertical sub-block without causing program disturb of memory cells that are not to receive programming.

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

Techniques are provided for pre-charging NAND strings during a programming operation. The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge phase of a programming operation, an overdrive voltage is applied to some memory cells and a bypass voltage is applied to other memory cells. The overdrive voltage allows the channel of an unselected NAND string to adequately charge during the pre-charge phase. Adequate charging of the channel helps the channel voltage to boost to a sufficient level to inhibit programming of an unselected memory cell during a program phase. Thus, program disturb is prevented, or at least reduced. The technique allows, for example, programming of memory cells in a middle vertical sub-block without causing program disturb of memory cells that are not to receive programming.

Techniques are provided for pre-charging NAND strings during a programming operation. The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge phase of a programming operation, an overdrive voltage is applied to some memory cells and a bypass voltage is applied to other memory cells. The overdrive voltage allows the channel of an unselected NAND string to adequately charge during the pre-charge phase. Adequate charging of the channel helps the channel voltage to boost to a sufficient level to inhibit programming of an unselected memory cell during a program phase. Thus, program disturb is prevented, or at least reduced. The technique allows, for example, programming of memory cells in a middle vertical sub-block without causing program disturb of memory cells that are not to receive programming.

A sensing circuit of nonvolatile memory device includes a precharge current generator, an adjusting transistor, and an adaptive control voltage generator. The precharge current generator connected to a sensing node and generates a precharge current provided to a bit-line of the nonvolatile memory device, in response to a precharge signal. The adjusting transistor, connected between the sensing node and a first node, adjusts an amount of the precharge current provided to the bit-line in response to a first control voltage. The adaptive control voltage generator generates a control current proportional to an operating temperature, in response to the precharge signal and a second control voltage and boosts a level of the first control voltage in proportion to the operating temperature. The second control voltage is inversely proportional to the operating temperature.