A random code generator includes a memory cell array and a sensing circuit. The memory cell array includes plural antifuse differential cells. The sensing circuit has an input terminal and an inverted input terminal. When a first antifuse differential cell of the memory cell array is a selected cell, a bit line of the selected cell is connected with the input terminal of the sensing circuit and an inverted bit line of the selected cell is connected with the inverted input terminal of the sensing circuit. During a read cycle, the sensing circuit judges a storage state of the selected cell according to a first charging current of the bit line and a second charging current of the inverted bit line, and determines a bit of a random code according to the storage state of the selected cell.

A non-volatile memory cell includes a first select transistor, a first floating gate transistor, a second floating gate transistor and a second select transistor. The first select transistor is connected with a program source line and a program word line. The first floating gate transistor includes a floating gate. The first floating gate transistor is connected with the first select transistor and a program bit line. The second floating gate transistor includes a floating gate. The second floating gate transistor is connected with a read source line. The second select transistor is connected with the second floating gate transistor, the read word line and the read bit line. The floating gate of the second floating gate transistor is connected with the floating gate of the first floating gate transistor.

Memories might include an array of memory cells including a string of series-connected split-gate memory cells, and a controller configured to cause the memory to selectively activate a first memory cell portion of a selected split-gate memory cell of the string of series-connected split-gate memory cells in response to a data state of the first memory cell portion of the selected split-gate memory cell and deactivate a second memory cell portion of the selected split-gate memory cell, and activate a second memory cell portion of each remaining split-gate memory cell of the string of series-connected split-gate memory cells while selectively activating the first memory cell portion of the selected split-gate memory cell and deactivating the second memory cell portion of the selected split-gate memory cell.

A non-volatile memory combines a data cell and a reference cell. The data cell includes a coupling structure and a transistor stack. The transistor stack is electrically coupled to the coupling structure. The data cell can store data and output a data signal that corresponds to the data. The reference cell includes a transistor stack that has the same structure as that of the data cell and outputs a reference signal. A column circuit is electrically coupled to the data cell and the first reference cell and configured to process the data signal using the reference signal.

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

A sensing circuit includes a sensing stage. The sensing stage includes a voltage clamp, a P-type transistor and an N-type transistor. The voltage clamp receives a first power supply voltage and generates a second power supply voltage. The source terminal of the P-type transistor receives the second power supply voltage. The gate terminal of the P-type transistor receives a cell current from a selected circuit of a non-volatile memory. The drain terminal of the N-type transistor is connected with the drain terminal of the P-type transistor. The gate terminal of the N-type transistor receives a bias voltage. The source terminal of the N-type transistor receives a ground voltage. In a sensing period, the second power supply voltage from the voltage clamp is fixed and lower than the first power supply voltage.

A semiconductor device includes first and second memory cells, a first word line, and a first and second bit lines, and a row control circuit. The first memory cell has a first gate electrode and a first channel having one end and another end. The second memory cell has a second gate electrode and a second channel having one end and another end. The first word line electrically connected with each of the first gate electrode and the second gate electrode. The first and second bit lines electrically connected with the first and second channels, respectively. When a threshold voltage of each of the first and second memory cells are caused to be shifted, the semiconductor device causes a first voltage between the first gate electrode and the first channel and a second voltage between the second gate electrode and the second channel to be differentiated.

An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. The memory cell comprises a select transistor and a floating gate transistor. The floating gate of the floating gate transistor and an assist gate region are collaboratively formed as a capacitor. The floating gate of the floating gate transistor and an erase gate region are collaboratively formed as another capacitor. Moreover, the select transistor, the floating gate transistor and the two capacitors are collaboratively formed as a four-terminal memory cell. Consequently, the size of the memory cell is small, and the memory cell is operated more easily.

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

Device and method of forming a non-volatile memory (NVM) device are disclosed. The NVM device includes NVM cells disposed on a substrate in a device region. The NVM cell includes a floating gate (FG) with first and second FG sidewalls disposed on the substrate and an intergate dielectric layer disposed over the FG and substrate. Re-entrants are disposed at corners of the intergate dielectric which are filled by dielectric re-entrant spacers. An access gate (AG) with first and second AG sidewalls is disposed on the substrate adjacent to the FG such that the second AG sidewall is adjacent to a first FG sidewall and separated by the intergate dielectric layer and the re-entrant spacers prevent AG from filling the re-entrants. A first source/drain (S/D) region is disposed in the substrate adjacent to the first AG sidewall and a second S/D region is disposed in the substrate adjacent to the second FG sidewall.