A semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells include at least one second transistor, where the control circuits control the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least one of the memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.

Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).

A storage circuit includes: the array of a memory cell MC including a variable-resistance element; a conversion circuit that converts the resistance value of each memory cell into the signal level of an electric signal; a reference signal generation circuit that generates a reference signal common to a plurality of columns; a correction circuit that corrects one of the signal level of the reference signal and the signal level of the electric signal for each column of the array of the memory cell; and an RW circuit that determines data stored in the memory cell belonging to a corresponding column by comparing one of the reference level and the signal level of the electric signal, corrected by the correction circuit, and the other of the reference level and the signal level of the electric signal.

A method for operating a memory includes: receiving a first write command and a first write address; receiving first write data a portion of which is masked; reading first read data and a first read error correction code from a region selected based on the first write address in a cell array; detecting and correcting an error in the first read data based on the first read error correction code to produce error-corrected first read data; generating first new write data by replacing the masked portion of the first write data with a portion of the error-corrected first read data; generating a first write error correction code based on the first new write data; and writing the first new write data and the first write error correction code into the region selected based on the first write address in response to the detecting of the error.

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

According to one embodiment, a memory system includes: a controller configured to execute an error correction process on first data read from a first area at a first address of a memory device and determine a read level used for reading data at the first address according to a result of the correction process. The controller executes the correction process on first frame data of the first data. When the correction process on the first frame data has failed, the controller executes the correction process on second frame data of the first data. When the correction process on the second frame data has succeeded, the controller determines the read level based on a result of comparison between the second frame data and a result of the correction process on the second frame data.

Disclosed herein are related to a system and a method of extending a lifetime of a memory cell. In one aspect, a memory controller applies a first pulse having a first amplitude to the memory cell to write input data to the memory cell. In one aspect, the memory controller applies a second pulse having a second amplitude larger than the first amplitude to the memory cell to extend a lifetime of the memory cell. The memory cell may include a resistive memory device or a phase change random access memory device. In one aspect, the memory controller applies the second pulse to the memory cell to repair the memory cell in response to determining that the memory cell has failed. In one aspect, the memory controller periodically applies the second pulse to the memory cell to extend the lifetime of the memory cell before the memory cell fails.

An integrated circuit die includes memory sectors, each memory sector including a memory array. The die includes a voltage regulator with a first transistor driven by an output voltage to thereby generate a gate voltage, the output voltage being generated based upon a difference between a constant current and a leakage current. A selection circuit selectively couples the gate voltage to a selected one of the plurality of memory sectors. A leakage detector circuit drives a second transistor with the output voltage to thereby generate a copy voltage based upon a difference between a variable current and a replica of the constant current, increases the variable current in response to the copy voltage being greater than the gate voltage, and asserts a leakage detection signal in response to the copy voltage being less than the gate voltage, the leakage detection signal indicating excess leakage within the memory array.

A storage device includes a memory device and a memory controller. The memory device stores a history read table including root bit information, read voltage information, and error bit information on each of a plurality of memory blocks, and performs a read operation of reading data stored in the plurality of memory blocks based on the history read table. When the read operation fails, a memory controller changes a level of a read voltage, and controls the memory device to perform a read retry operation of retrying the read operation by using the changed read voltage. When the read retry operation passes, the memory controller determines whether the history read table is to be updated by comparing the root bit information of the read retry operation with the root bit information of the history read table.