A stand-alone active thermal interposer device for use in testing a system-in-package device under test (DUT), the active thermal interposer device includes a body layer having a first surface and a second surface, wherein the first surface is operable to be disposed adjacent to a cold plate, and a plurality of heating zones defined across a second surface of the body layer, the plurality of heating zones operable to be controlled by a thermal controller to selectively heat and maintain respective temperatures thereof, the plurality of heating zones operable to heat a plurality of areas of the DUT when the second surface of the body layer is disposed adjacent to an interface surface of the DUT during testing of the DUT.

A feedback burn-in device of a burn-in oven includes at least one burn-in rack disposed in the burn-in oven, at least one burn-in board, and at least one feedback burn-in unit. The burn-in rack is formed, in a top thereof, with at least one horizontal ventilation passage in communication with an interior of the burn-in rack. The horizontal ventilation passage has an end connected to at least one negative pressure zone or heat dissipation blower of the burn-in oven. The burn-in board is disposed in the interior of the burn-in rack. The burn-in board is connected to a socket to which at least one tested IC is connectable. The feedback burn-in unit is connected to the socket and the burn-in board. The feedback burn-in unit provide automatic feedback control for a burn-in board environment temperature, tested IC temperature detection, and a tested IC burn-in temperature, a dissipating airflow speed, and a burn-in board environment temperature, so as to discharge heat-dissipation hot air from the burn-in board and the tested IC of each feedback burn-in unit to the horizontal ventilation passage of the burn-in rack to be further discharge through one end of the horizontal ventilation passage to a negative pressure zone or a discharge blower of the burn-in oven, thereby forming a feedback burn-in device featuring automatic feedback burn-in and heat dissipative airflow discharged to the burn-in oven.

A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.

A testing equipment includes a testing platform and a component carrying device including a carrying arm, a vacuum suction unit, a working bottom cover and a fluid transmission assembly. The carrying arm lifts and carries a device under test (DUT) onto the testing platform. The vacuum suction unit removably sucks to the DUT. The working bottom cover includes a cover body and an elastic airtight ring. The cover body is connected to the carrying arm, and the elastic airtight ring is fixedly disposed on the cover body for hermetically covering the DUT, so that a liquid filling space is collectively formed by the cover body and the DUT. The fluid transmission assembly extends into the liquid filling space for continuously passing a working liquid to the DUT and withdrawing the working liquid back away from the liquid filling space for thermally exchanging with the DUT.

A system for testing circuits of an integrated circuit semiconductor wafer includes a tester system for generating signals for input to the circuits and for processing output signals from the circuits for testing the wafer and a test stack coupled to the tester system. The test stack includes a wafer probe for contacting a first surface of the wafer and for probing individual circuits of the circuits of the wafer, a wafer thermal interposer (TI) layer operable to contact a second surface of the wafer and operable to selectively heat areas of the wafer, and a cold plate disposed under the wafer TI layer and operable to cool the wafer. The system further includes a thermal controller for selectively heating and maintaining temperatures of the areas of the wafer by controlling cooling of the cold plate and by controlling selective heating of the wafer TI layer.

A method for testing a semiconductor chip that has a pn junction constituting a parasitic diode therein includes: causing probe terminals to be in contact with front surface electrodes of the semiconductor chip; obtaining a temperature of the semiconductor chip by measuring electrical characteristics of the parasitic diode through at least one of the front surface electrodes and a back surface electrode and by referring to prescribed temperature characteristics of the parasitic diode; if the obtained temperature is not within a prescribed tolerance from the predetermined target temperature, heating up the semiconductor chip by applying voltage between one or more of the front surface electrodes and the back surface electrode; and once the obtained temperature increases and reaches the predetermined target temperature within the prescribed tolerance, testing electrical characteristics of the semiconductor chip through the front surface electrodes and the back surface electrode.

The present invention relates to a method for exchanging heat with an object said method comprising using a heat transfer fluid wherein said heat transfer fluid comprises one or more chemical compounds having the general formula (I) wherein: —R.sub.f can be any C.sub.1-C.sub.10 fluorinated linear or branched carbon chain which can be partially or fully fluorinated, and can comprise O or S atoms, —X, Y and Z can be independently selected from halogens or hydrogen, with the provision that at least one of X, Y or Z is a halogen.

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A method for assessing the state of damage of a semiconductor module that is subject to operational loading, in particular a semiconductor module of a drive system converter, that includes at least one semiconductor component arranged on or in a support structure. It is possible not only to estimate a spent service life for the entire semiconductor module, but also to detect unexpected or undesirable loading states and thus a premature reduction of the remaining service life of the semiconductor module. Continuous load assessments are thus possible already during the operation of the semiconductor module and allow interventions to be made in good time.

A testing apparatus for Devices Under Test (DUTs) includes at least one intake damper and at least one exhaust damper. At least one fan moves recirculated fluid and exterior fluid across one or more DUTs inside the testing apparatus. In one aspect, the testing apparatus includes a door to provide access to a chamber and the door includes at least one channel. At least a portion of the fluid flows through the at least one channel of the door. In another aspect, the door is configured to provide access to a chamber from the front of the chamber and the fluid is moved in a direction across the one or more DUTs substantially from the front of the chamber towards a rear of the chamber.

A chip testing system includes a central control device, a chip mounting apparatus, a plurality of environment control apparatus, a classification apparatus, and a transferring apparatus. The central control device is configured to control the chip mounting apparatus to dispose a plurality of chips onto a chip testing device. Each of the environment control apparatus includes a plurality of accommodating chambers that are independent from each other. Each of the accommodating chambers is provided with a temperature adjusting device. The central control device is configured to control the transferring apparatus to place the chip testing device into one of the accommodating chambers. When the chip testing device carrying the chips is arranged in the corresponding accommodating chamber, the central control device is configured to control an operation of the corresponding temperature adjusting device, so that the chips are in an environment of a predetermined temperature.