A sensor device comprises a sensor connected to a first signal and responsive to an external field to produce a sensor signal, a test device connected to a second signal and electrically connected in series with the sensor by an electrical test connection providing a test signal, and a monitor circuit electrically connected to the first, second and test signals. The monitor circuit comprises a processing circuit and a determination circuit. The processing circuit is responsive to the test signal and a predetermined processing value to form a processing output signal. The determination circuit is responsive to the processing output signal to determine a diagnostic signal. A sensor circuit responsive to the sensor signal provides a sensor device signal responsive to the external field.

An integrated circuit, IC, comprising one or more DC blocking modules connected to a respective input/output, IO, pin of the IC, each DC blocking module comprising: a capacitor having a first terminal connected to the respective IO pin and a second terminal connected to a node of the circuitry of the IC; and an electrostatic discharge, ESD, protection circuit connected in parallel to the capacitor, the ESD protection circuit comprising: a conduction path connected between the first terminal of the capacitor and the second terminal of the capacitor; and a control terminal configured to receive a control signal to switch the ESD protection circuit between: an operational mode in which the conduction path is in a non-conducting state and provides ESD protection to the capacitor; and a test mode in which the conduction path is in a conducting state and short circuits the capacitor.

A testkey includes two switching circuits and two compensation circuits. The first switching circuit transmits a test signal to a first DUT when the first DUT is being tested and functions as high impedance when the first DUT is not being tested. The second switching circuit transmits the test signal to a second DUT when the second DUT is being tested and functions as high impedance when the second DUT is not being tested. When the first DUT is not being tested and the second DUT is being tested, the first compensation circuit provides first compensation current for reducing the leakage current of the first switching circuit. When the first DUT is being tested and the second DUT is not being tested, the second compensation circuit provides second compensation current for reducing the leakage current of the second switching circuit.

A test system of embodiments electrically connects one or more first semiconductor chips formed on a first wafer and one or more second semiconductor chips formed on a second wafer to perform tests on the one or more first and second semiconductor chips. The test system includes a test device that supplies a test signal to each of the one or more first semiconductor chips, a first probe device including a first probe to be connected to a first internal pad of each of the one or more first semiconductor chips and a first communication circuit configured to transmit and receive a signal, and a second probe device including a second probe to be connected to a second internal pad of each of the one or more second semiconductor chips and a second communication circuit configured to transmit and receive the signal to and from the first communication circuit.

Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

Systems and methods for improving substrate fabrication are provided. Subsets of dies of substrates may be inspected at various points in the fabrication process to generate spectra data. The spectra data can be used to generate data that are input to a machine learning model to predict yields for the substrates.

The first logic wafer is attached to a supporting wafer, which adds sufficient depth to this bonded structure such that the first logic wafer may be thinned during the manufacturing process. The first logic wafer is thinned such that the through silicon vias may be etched in the substrate of the first logic wafer so as to provide adequate connectivity to a second logic wafer, which is bonded to the first logic wafer. The second logic wafer adds sufficient depth to this bonded structure to allow the supporting wafer to then be thinned to enable through silicon vias to be added to the supporting wafer so as to provide appropriate connectivity for the entire stacked structure. The thinned supporting wafer is retained in the finished stacked wafer structure and may comprise additional components (e.g. capacitors) supporting the operation of the processing circuitry in the logic wafers.

A wafer inspection method and inspection apparatus that perform a voltage inspection of a die on a wafer by a probe module. The probe module includes a processing module, a first probe coupled to a first electrode point of the die, and a second probe coupled to a second electrode point of the die. The first probe is coupled to the processing module, and the second probe is grounded. The processing module provides the die with a driving current through the first probe, and obtains an inspection voltage corresponding to the die. The processing module generates an inspection result of the inspection voltage based on two reference voltages respectively representing a high critical threshold value and a low critical threshold value of the die under a normal operation. The inspection result indicates an operating status of the die. Thus, inspection costs are reduced and inspection efficiency is enhanced.

A method of identifying defects in an electronic assembly, comprising, by a processing unit, obtaining a grid of nodes representative of a location of electronic units of an electronic assembly, wherein each node is neighboured by at most eight other nodes, wherein a first plurality of nodes represents failed electronic units according to at least one test criterion, and a second plurality of nodes represents passing electronic units according to the least one first test criterion, based on the grid, determining at least one first and second straight lines, and attempting to connect the first and second straight lines into a new line, wherein if at least one node from the new line belongs to the second plurality of nodes, concluding that an electronic unit represented by the node on the grid is a failed electronic unit, thereby facilitating identification of a failed electronic unit on the substrate.

A wafer chip testing method and apparatus, an electronic device and a storage medium are provided. The testing method includes: comparing each configuration parameter of each wafer chip with a standard specification threshold interval of a corresponding parameter type, and marking as marked test parameters configuration parameters which do not belong to the standard specification threshold intervals; and inputting all marked test parameters of individual wafer chip into a combination rule judgment function respectively, outputting wafer chip(s) which does not conform to any one or more rules in the combination rule judgment function, and determining the wafer chip(s) as unqualified wafer chip(s).