A waveguide connection structure consists of a waveguide chip having a waveguide, and a connector having a groove dug in a thickness direction, the waveguide chip and the connector each having a concave-convex portion that fit into each other in a state of being adjacent to each other on the same plane.

A package includes a photonic integrated circuit die, an electric integrated circuit die, and an encapsulant. The photonic integrated circuit die includes a semiconductor substrate, an insulation layer, and a waveguide. The semiconductor substrate has a notch. The insulation layer is disposed on the semiconductor substrate. The waveguide is disposed on the insulation layer. The notch of the semiconductor substrate is underneath at least a portion of the waveguide. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The encapsulant laterally encapsulates the electric integrated circuit die.

A photonic integrated circuit may be coupled to an optical fiber and packaged. The optical fiber may be supported by a fiber holder during a solder reflow process performed to mount the packaged photonic integrated circuit to a circuit board or other substrate. The optical fiber may be decoupled from the fiber holder, and the fiber holder removed, after completion of the solder reflow process.

Photonic integrated circuits (PICs) enable manipulation of light on a chip for telecommunications and information processing. They can be made with silicon and silicon-compatible materials using complementary metal-oxide-semiconductor (CMOS) fabrication techniques developed for making electronics. Unfortunately, most light sources are made with III-V and II-VI materials, which are not compatible with silicon CMOS fabrication techniques. As a result, the light source for a PIC is either off-chip or integrated onto the PIC after CMOS fabrication is over. Hybrid integration can be improved by forming a recess in the PIC to receive a III-V or II-VI photonic chip. Mechanical stops formed in or next to the recess during fabrication align the photonic chip vertically to the PIC. Fiducials on the PIC and the photonic chip enable sub-micron lateral alignment. As a result, the photonic chip can be flip-chip bonded to the PIC with sub-micron vertical and lateral alignment precision.

An integrated circuit package and a method of forming the same are provided. The integrated circuit package includes a photonic integrated circuit die. The photonic integrated circuit die includes an optical coupler. The integrated circuit package further includes an encapsulant encapsulating the photonic integrated circuit die, a first redistribution structure over the photonic integrated circuit die and the encapsulant, and an opening extending through the first redistribution structure and exposing the optical coupler.

Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

A semiconductor optical device includes: a laser for emitting light; a modulator for modulating the light using an electroabsorption effect; a chip capacitor that is electrically connected in parallel to the laser; a chip inductor that is electrically connected in series to the chip capacitor, is electrically connected in series to the laser and the chip capacitor as a whole, and includes a first terminal and a second terminal; a solder or a conductive adhesive that directly bonds the first terminal of the chip inductor and the chip capacitor to each other; an electrical wiring group in which the laser, the modulator, the chip capacitor, and the chip inductor are electrically connected to each other; and a substrate on which the laser, the modulator, the chip capacitor, and the chip inductor are mounted.

Techniques for efficient alignment of a semiconductor laser in a Photonic Integrated Circuit (PIC) are disclosed. In some embodiments, a photonic integrated circuit (PIC) may include a semiconductor laser that includes a laser mating surface, and a substrate that includes a substrate mating surface. A shape of the laser mating surface and a shape of the substrate mating surface may be configured to align the semiconductor laser with the substrate in three dimensions.

A structure and method of formation of a buried heterostructure laser die with alignment aids wherein the alignment aids include lateral and vertical structures formed on the die. Lateral alignment aids are formed using a same mask layer as the ridge structure of the laser and provide fiducials that are formed in reference to the ridge structure. Vertical alignment aids, and vertical protrusions of the lateral alignment aids are formed using etch stop layers positioned in the buried heterostructure laser layer structure.

An interconnect system includes a first circuit board, first and second connectors connected to the first circuit board, and a transceiver including an optical engine and arranged to receive and transmit electrical and optical signals through a cable, to convert optical signals received from the cable into electrical signals, and to convert electrical signals received from the first connector into optical signals to be transmitted through the cable. The transceiver is arranged to mate with the first and second connectors so that at least some converted electrical signals are transmitted to the first connector and so that at least some electrical signals received from the cable are transmitted to the second connector.