Apparatus and methods are disclosed for providing a bias, comprising a bias generator circuit including a high voltage (HV) circuit configured to generate a regulated high voltage (HV) from an HV line and provide the regulated HV at an HV regulated line and a low voltage (LV) circuit configured to generate a low voltage (LV) differential from the HV line and to provide the LV differential at an LV line, wherein the LV circuit is configured to direct current used to generate the LV differential into the HV regulated line.

Apparatus and methods are disclosed for providing a bias, comprising a bias generator circuit including a high voltage (HV) circuit configured to generate a regulated high voltage (HV) from an HV line and provide the regulated HV at an HV regulated line and a low voltage (LV) circuit configured to generate a low voltage (LV) differential from the HV line and to provide the LV differential at an LV line.

A method for an improved characterization of standard cells in a circuit design process is disclosed. Adaptive body biasing is considered during the design process by using simulation results of a cell set, a data-set for performance of the cell set, and a data-set for a hardware performance for a slow, typical and fast circuit property. Static deviations in a supply voltage are considered by determining a reference performance of a cell and a reference hardware performance monitor value at a PVT corner. A virtual regulation and adapting of body bias voltages of the cell set is performed such that the reference performance of the cell or the reference hardware performance monitor value will be reached at each PVT corner and for compensating the static deviation in the supply voltage. The results are provided in a library file.

Techniques and architectures for simultaneous readout and integration of image data from pixels while increasing their sensitivity and reducing required data rates for moving information off of the chip using pixels configured to conduct Analog-to-Digital Conversions (ADCs) of image data, wherein each pixel operates in a rolling Integrate While Read (IWR) mode using SRAM in place of traditional latches for in-pixel storage.

A control circuit and a delay circuit are provided. The control circuit includes a control unit and a feedback unit. The feedback unit is configured to output a feedback signal according to a voltage of the control unit and a reference voltage; a first terminal of the feedback unit is connected to a first terminal of the control unit, a second terminal of the feedback unit serves as an input terminal of the reference voltage, and an output terminal of the feedback unit is connected to a second terminal of the control unit. The control unit is configured to adjust a voltage of the second terminal of the control unit according to the feedback signal, so as to allow a current variation of the control unit with a first parameter to be within a first range.

Disclosed is an integrated circuit including a first bias current generating circuit. The first bias current generating circuit includes a first amplifier receiving a reference voltage and a first voltage and amplifying a difference between them to output a first output voltage, a first bias current generator receiving the first output voltage and outputting a first bias current in response to the first output voltage, a variable resistor receiving the first bias current and outputting the first voltage in response to the first bias current and a calibration code, a second bias current generator receiving the first output voltage and outputting a second bias current to a peripheral circuit in response to the first output voltage, and a third bias current generator receiving the first output voltage and outputting a third bias current to an external device through a first pad in response to the first output voltage.

A semiconductor circuit and a method of operating the same are provided. The semiconductor circuit comprises a first digital-to-analog converter configured to generate a first output current in response to a first binary code, and a second digital-to-analog converter configured to generate a second output current in response to a second binary code associated with the first binary code. The semiconductor circuit further comprises a first current-to-voltage converter configured to generate a first candidate voltage based on the first output current, and a second current-to-voltage converter configured to generate a second candidate voltage based on the second output current. The semiconductor circuit further comprises a multiplexer configured to output the target voltage based on the first candidate voltage or the second candidate voltage. The target voltage includes a configurable range associated with the second binary code.

The present disclosure provides a circuit for generating a complimentary to absolute temperature (CTAT) voltage reference. The primary contributor to the voltage reference is first bipolar junction transistor, which is configured in diode mode, to produce the CTAT voltage. Such references include a non-linear component. A pair of bipolar junction transistors are coupled to the first bipolar junction transistor, and are configured to generate a delta base-emitter voltage. By coupling one of the pair to a proportional to absolute temperature current source, and the other to a current course which is substantially independent of absolute temperature, a further non-linear component is introduced, which is complimentary to the non-linear component introduced by the first bipolar junction transistor. The pair of bipolar transistors share a common emitter area size. As such, the non-linear component of the first bipolar junction transistor is compensated by the delta base-emitter arrangement, resulting in a more linear output.

A voltage regulation integrated circuit (IC) includes a first transistor, a feedback circuit, a bias circuit, an amplifier circuit, and a transient coupling circuit. The first transistor is configured to generate an output voltage according to an input voltage and a control voltage. The feedback circuit is configured to generate a feedback voltage according to the output voltage. The output voltage includes an AC component. The bias circuit is configured to generate a first bias voltage. The amplifier circuit is configured to generate the control voltage according to the first bias voltage and the feedback voltage. The transient coupling circuit is configured to generate a coupling voltage according to the AC component and to assist the change of the first bias voltage according to the coupling voltage, so that the output voltage is maintained at a voltage level.

A method and an apparatus for reducing an effect of local process variations of a digital circuit on a hardware performance monitor includes measuring a set of performance values (c.sub.1, c.sub.2 . . . c.sub.n) of the digital circuit by n identical hardware performance monitors, where n is a natural number greater than 1, determining an average value c.sub.mean of the measured performance values (c.sub.1, c.sub.2 . . . c.sub.n), as an approximation of an ideal performance value c.sub.0, selecting one performance value c.sub.j of the set of performance values (c.sub.1, c.sub.2 . . . c.sub.n) by a controller, comparing the performance value c.sub.j with a reference value c.sub.ref by a controller the controller, resulting in a deviation value Δc, and controlling an actuator by using the deviation Δc for regulating the local global process variations to the approximation c.sub.mean of the ideal performance value c.sub.0.