Programmable temperature regulation circuits, and methods of operating programmable temperature regulation circuits, are disclosed for providing heat to a target area on a chip. The programmable temperature regulation circuits include a heating element on the chip, and a regulation loop operatively connected to the heating element. The regulation loop includes a first diode that measures the temperature in the target area, and an operational transconductance amplifier. The operational transconductance amplifier receives a reference temperature voltage from a reference voltage, and a temperature feedback voltage from the diode, and generates an output voltage to control the provision of electrical power to the heating element.

A thermally-isolated-metal-oxide-semiconducting (TMOS) sensor has inputs coupled to first and second nodes to receive first and second bias currents, and an output coupled to a third node. A tail has a first conduction terminal coupled to the third node and a second conduction terminal coupled to a reference voltage. A control circuit applies a control signal to a control terminal of the tail transistor based upon voltages at the first and second nodes so that a common mode voltage at the first and second nodes is equal to a reference common mode voltage. A differential current integrator has a first input terminal coupled to the second node and a second input terminal coupled to the first node, and provides an output voltage indicative of an integral of a difference between a first output current at the first input terminal and a second output current at the second input terminal.

A start-up circuit includes series-connected first-type first transistors through which a start-up current flows in a start-up period, being connected between a positive power voltage and an inner node; and a first-type second transistor through which a boost current flows in the start-up period, being connected between the positive power voltage and the inner node, and with a gate connected to an output node that provides a bias voltage.

A start-up circuit includes series-connected first-type first transistors through which a start-up current flows in a start-up period, being connected between a positive power voltage and an inner node; and a first-type second transistor through which a boost current flows in the start-up period, being connected between the positive power voltage and the inner node, and with a gate connected to an output node that provides a bias voltage.

Provided are an LDO, an MCU, a fingerprint module and a terminal device. The LDO includes: a reference voltage generating circuit and a source follower connected to the reference voltage generating circuit. The reference voltage generating circuit is used to generate a reference voltage that changes with temperature to offset a voltage change caused by a voltage between a first terminal and a second terminal of the source follower changing with time, so that an output voltage of the second terminal of the source follower does not change with temperature. The LDO omits an operational amplifier EA and a resistor divider feedback network in the prior art, which not only has a simple circuit structure, but also can achieve ultra-low power consumption.

There is provided a current limiting diode comprising a gate, a source, and a drain electrically connected to the source by an n-channel or p-channel; wherein the source and the gate are electrically connected by a fill structure comprising a phase-change fill material, and wherein the phase-change fill material is configured to absorb heat from the n-channel or p-channel by changing phase.

A multi-channel current pulse generator for driving a plurality of loads with unique positive terminals and a shared negative terminal. The pulse generator comprises a pulse control transistor and, for each load, a load capacitor and a charging control transistor. The pulse control transistor allows or blocks current pulses through the loads and has a drain terminal connected to the shared negative terminal, a source terminal connected to ground, and a gate terminal for receiving a load driver control signal. The load capacitors are discharged by current pulses through the corresponding loads. The charging control transistors allow or block charging currents for the corresponding load capacitors. The pulse control transistor is preferably an enhancement mode GaN FET and is chosen to withstand current pulses through a maximum number of loads to be driven simultaneously.

A multi-channel current pulse generator for driving a plurality of loads with unique positive terminals and a shared negative terminal. The pulse generator comprises a pulse control transistor and, for each load, a load capacitor and a charging control transistor. The pulse control transistor allows or blocks current pulses through the loads and has a drain terminal connected to the shared negative terminal, a source terminal connected to ground, and a gate terminal for receiving a load driver control signal. The load capacitors are discharged by current pulses through the corresponding loads. The charging control transistors allow or block charging currents for the corresponding load capacitors. The pulse control transistor is preferably an enhancement mode GaN FET and is chosen to withstand current pulses through a maximum number of loads to be driven simultaneously.

Disclosed are a temperature compensation apparatus and method. The apparatus includes a reference signal generator that supplies at least one of a first current which is constant regardless of temperature variation and a second current which is proportional to temperature variation, a slope amplifier that determines a first output current having a second temperature coefficient which is a multiple of a first temperature coefficient of the second current, based on the first current and the second current, and a slope controller that determines a second output current having a third temperature coefficient, using a weighted average of the first current and the second current.

A reference stage includes a first transistor, a second transistor and a resistor that are connected in series from a voltage rail to a reference load. The resistor has (i) a resistance that is a function of a digital resistance-controlling value, (ii) a first terminal coupled to a gate of the first transistor, and (iii) a second terminal that has a voltage VG2 and is coupled to a gate of the second transistor. A comparator has a first input that is coupled to the resistor's second terminal. A diode-connected reference transistor is connected from the voltage rail to the comparator's second input to apply a voltage VD at the second input. An adjusting circuit adjusts the digital resistance-controlling value to cause VG2 to approach VD until the comparator's output changes state when VG2 reaches VD.