Patent classifications
G06F3/068
STORAGE SYSTEM AND METHOD FOR BURST MODE MANAGEMENT USING TRANSFER RAM
A storage system uses consumption of transfer RAM as a trigger to enter and exit burst mode. In one embodiment, the storage system stores, in volatile memory, data to be written in non-volatile memory; monitors an allocation level of the volatile memory to determine a first amount of time that the allocation level is at a first level and a second amount of time that the allocation level is at second level; enters burst mode when a ratio of the first amount of time and the second amount of time is above a first threshold; and exits burst mode when the ratio of the first amount of time and the second amount of time is below a second threshold. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
METHOD FOR REDUCING USE OF DRAM IN SSD AND THE SSD USING THE SAME
A SSD and a method for reducing use of DRAM in the SSD are disclosed. The method includes the steps of: A. providing a referring table in a DRAM module of a SSD; B. providing a logical-to-physical address table in the DRAM module; C. receiving a command for accessing a target data in a target logical address of the SSD; D. checking if one physical address is stored in the logical-to-physical address table; E. executing the command by using the mapping data in the subgroup or copying a corresponding subgroup including one mapping data for the target logical address from the mapping table to the DRAM module via the referring table; and; and F. adding a target physical address of the DRAM module where the mapping data for the target logical address is stored to the logical-to-physical address table so that the target logical address is able to correspond thereto.
Internal Data Transfer Management in a Hybrid Data Storage Device
Apparatus and method for managing data in a hybrid data storage device. In some embodiments, the hybrid data storage device has a hard disc drive (HDD) controller circuit coupled to non-volatile rotatable storage media and a solid state drive (SSD) controller circuit coupled to non-volatile solid state memory. A local memory stores a map structure which identifies logical addresses of current version data sets stored in the solid state memory. A top level controller circuit operates responsive to the map structure to direct a selected host data transfer access command to the HDD or SSD controller circuit. The map structure may be arranged as a plurality of discrete logical address sequences, where a gap is provided between each adjacent pair of the discrete logical address sequences in the map structure.
Hybrid Data Storage Device with Embedded Command Queuing
Apparatus and method for managing data in a hybrid data storage device. In some embodiments, a hybrid device has a hard disc drive (HDD) controller circuit coupled to non-volatile rotatable storage media and a solid state drive (SSD) controller circuit coupled to non-volatile solid state memory. A top level controller circuit directs a first portion of the received access commands to the HDD controller circuit and a second portion of the received access commands to the SSD controller circuit. The top level controller circuit performs an embedded queuing operation to forward internally generated data cleaning commands to an HDD command queue to write data previously transferred from the host device to the solid state memory to the rotatable storage media concurrently while least one of the first portion of the access commands is pending in the HDD command queue.
System, method and apparatus for accelerating fast block devices
A device, method and system is directed to fast data storage on a block storage device. New data is linearly written to an empty write block. A location of the new data is tracked. Meta data associated with the new data is linearly written. A lookup table may be updated based in part on the meta data. The new data may be read based the lookup table configured to map a logical address to a physical address.
Latency and throughput centric reconfigurable storage device
A storage device includes: a storage controller to receive data from a host device, and to store the data in storage memory; and a reconfigurable integrated circuit communicably connected to the storage controller, and to accelerate logic operations executed on the data stored in the storage memory, the reconfigurable integrated circuit including: a first logic block to execute a static logic operation from among the logic operations; a second logic block to execute one or more dynamic logic operations from among the logic operations; and a plurality of memory buffers configured to store inputs and outputs of the first and second logic blocks.
Data Write Control Apparatus and Method
A data write control method includes detecting a quantity of dirty blocks in a first memory when a write control apparatus is in write-back mode; separately predicting execution progress of a program run by a processor within a danger time period in the two write modes when the quantity of dirty blocks reaches a first preset threshold; when it is predicted that the execution progress of the program run by the processor within the danger time period in write-through mode is faster than the execution progress of the program run by the processor within the danger time period in write-back mode, switching a current data write mode to the write-through mode; and detecting the quantity of dirty blocks when the write control apparatus is in write-through mode and switching the current data write mode to the write-back mode when the quantity of dirty blocks decreases to a second preset threshold.
Elastic buffer based asymmetric pipeline FIFO process
The present disclosure generally relates to efficient management of an elastic buffer. Efficient management can be achieved by using an asymmetric asynchronous First In, First Out (FIFO) approach based on normalization of write and read pointers. The normalization is done in accordance with the FIFO depth while keeping a single bit change approach. In order to achieve an asymmetric dynamic ability for part per million (PPM) compensation, a plurality of sub-FIFOs are used for opponent side pointer synchronization. Combining the features allows for creating an asynchronous asymmetric FIFO with pipeline characteristics.
Hybrid memory management apparatus and method for many-to-one virtualization environment
Disclosed herein are a hybrid memory management apparatus and method for an many-to-one virtualization environment. The hybrid memory management apparatus is implemented in an inverse-virtualization-based multi-node computing system including multiple physical nodes, each containing hybrid memory in which DRAM and NVRAM coexist, a virtual machine, and hypervisors, and includes memory for storing at least one program, and a processor for executing the program, wherein the program includes a remote request service module for processing a page-related request with reference to the hybrid memory and responding to the page-related request by transmitting a result of processing, an internal request service module for processing an internal page fault request with reference to a hybrid memory and responding to the internal page fault request, and a data arrangement module for responding to an inquiry request for a location at which a newly added page is to be arranged in the hybrid memory.
Command Tunneling in a Hybrid Data Storage Device
Apparatus and method for managing data in a hybrid data storage device. In some embodiments, a hybrid device has a hard disc drive (HDD) controller circuit coupled to non-volatile rotatable media and a solid state drive (SSD) controller circuit coupled to non-volatile solid state memory. A top level controller circuit directs a selected access command one of the HDD controller circuit or the SSD controller circuit responsive to a selected parameter associated with the selected access command. In a normal mode, the top level controller circuit directs a transfer of data between the host and the HDD controller circuit and handles host interface communications. In a tunneling mode, the top level controller circuit directly connects the HDD controller circuit to the host device. In this way, tunnel mode bypasses processing operations required by the top level controller circuit. Tunnel mode and normal mode may be selected on a command-by-command basis.