A data storage device includes a shared command queue, a queue controller, a processor, and a memory. The command queue is configured to queue a plurality of jobs transmitted from a plurality of host processors. The queue controller is configured to classify the plurality of jobs into a plurality of levels of jobs according to priority threshold values and assign jobs of the plurality of levels of jobs the processor. The processor is configured to process the jobs assigned by the queue controller. The memory may store data needed to process the job.

A memory sub-system configured to dynamically generate a media layout to avoid media access collisions in concurrent streams. The memory sub-system can identify plurality of media units that are available to write data concurrently, select commands from the plurality of streams for concurrent execution in the available media units, generate and store a portion of a media layout dynamically in response to the commands being selected for concurrent execution in the plurality of media units, and executing the selected commands concurrently by storing data into the memory units according to physical addresses to which logical addresses used in the selected commands are mapped in the dynamically generated portion of the media layout.

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

A method for mapping LUNs (logical unit numbers) in storage memory, performed by a storage system, is provided. The method includes determining a set of LUNs in the storage memory and generating a mapping from a logical address space to all of the LUNs in the set, based on the determining, so that each logical address in the logical address space maps to one LUN in the set. The method includes accessing one or more of the LUNs in accordance with the mapping.

Embodiments relate to the field of storage technologies. The method is applied to a flash device whose first physical storage space stores a data block at a first security level and a data block at a second security level and whose second physical storage space stores a data block at a second security level. The method includes: receiving a data write request used to request to write target data, and obtaining a security level of the target data; and writing the target data into the first physical storage space if the security level of the target data is the first security level; or writing the target data into the second physical storage space or writing the target data into the second physical storage space and the first physical storage space if the security level of the target data is the second security level.

A memory controller includes: a block manager for allocating a plurality of partial super blocks each including partial blocks in different memory blocks; and an operation controller for controlling a plurality of memory devices to perform, in parallel, a program operation of sequentially storing data in physical pages in each of the partial blocks in a partial super block selected from the plurality of partial super blocks. Each of the plurality of partial super blocks includes partial blocks in memory blocks having different numbers of physical pages having an erase state.

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

Systems and methods for storing data are described. A system can comprise a controller, one or more physical non-volatile memory devices, a bus comprising a plurality of input/output (I/O) lines. The controller configured to receive data, encode the received data into a codeword, and transfer, in parallel, different portions of the codeword to different physical non-volatile memory devices among the plurality of physical non-volatile memory devices.

Examples herein describe hardware architecture for processing and accelerating data passing through layers of a neural network. In one embodiment, a reconfigurable integrated circuit (IC) for use with a neural network includes a digital processing engine (DPE) array, each DPE having a plurality of neural network units (NNUs). Each DPE generates different output data based on the currently processing layer of the neural network, with the NNUs parallel processing different input data sets. The reconfigurable IC also includes a plurality of ping-pong buffers designed to alternate storing and processing data for the layers of the neural network.

According to one embodiment, a memory system includes a volatile memory, a power supply circuit, and a controller. The power supply circuit includes a first power supply path in which power supplied from a host device is supplied to the volatile memory, a second power supply path in which the power is supplied from the internal power supply to the volatile memory, and a switching device that switches between the first power supply path and the second power supply path. In response to an instruction for a transition to a low power consumption mode received from the host device, the controller outputs, to the switching device, an instruction to switch the power supply circuit from the first power supply path to the second power supply path.