A storage system manages correspondence relationships between physical addresses and logical addresses inside a storage device, as well as logical spaces provided by a plurality of storage devices, and when a determination is made as to whether first data and second data are stored in the same storage device in a case in which the first data and the second data are exchanged inside a logical space, and the determination is found to be affirmative, the storage device replaces the logical address corresponding to the first data with the logical address corresponding to the second data without changing the physical address of the physical area in which the first data is stored and the physical address of the physical area in which the second data is stored.

An apparatus is described. The apparatus can include non-volatile memory, an embedded processor, and a memory controller. The memory controller can access data from the byte addressable non-volatile memory using at least one of: a first addressing scheme or a second addressing scheme. The memory controller can provide the data to a host system over a first interface when the data is accessed using the first addressing scheme. The memory controller can provide the data to the embedded processor over a second interface when the data is accessed using the second addressing scheme.

An apparatus having a first interface of a first type supporting a plurality of data ports, a second interface of a second type supporting at least a portion of the plurality data ports, and a third interface of the second type. The apparatus also including a switching module coupled to a control port of the first interface and configured for selectably coupling the plurality of data ports to at least one of the second interface and the third interface based on a signal at the control port.

Variables utilized in device firmware that provides various boot and runtime services are repaved in a fault-tolerant manner within a secure store in a durable, non-volatile device memory during an FOTA update process. A spare region in the secure store is utilized to temporarily hold a back-up of a primary region in which the firmware variables are written. Using a transaction-based fault-tolerant write (FTW) process, the variables in the primary region can be repaved with variables contained in a firmware update payload that is delivered from a remote service. In the event of a fault in the variable region repaving process, either the primary or spare region will remain valid so that firmware in a known good state can be utilized to enable the device to boot successfully and the variable region repaving in the FOTA update process may be restarted.

A mapping table updating method, a memory control circuit unit and a memory storage device are provided. The mapping table updating method includes: recording first mapping information as a mapping relation between a first virtual block and a first physical erasing unit; recording second mapping information as a mapping relation between the first virtual block and a second virtual block, and the second virtual block is mapped to the first physical erasing unit; and updating the second mapping information as a mapping relation between the first virtual block and a third virtual block if copying data belonging to the first physical erasing unit to a second physical erasing unit, and the third virtual block is mapped to the second physical erasing unit.

According to an embodiment, when a storage status of a first storage unit is recognized as a protected state, a control unit writes data to a second storage unit. When a read target address is recorded in a data migration log area, the control unit reads data from the second storage unit. When the read target address is not recorded in the data migration log area, the control unit reads data from the first storage unit.

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

The over-provisioning (OP) of a physical storage device (PSD) may be increased, and the useful life of the PSD increased, by converting uncompressed data stored on the PSD to compressed data. It may be determined that increasing the useful life of the PSD, and the data reduction resulting from the compression, outweigh the benefit of faster I/O response times if the data remains uncompressed. A first portion of the PSD may be initially reserved for compression. A second portion of the PSD may store compressed data. It may be determined whether it is desirable to increase the OP of the PSD to thereby reduce the effective write rate on the PSD. If compression is determined to be desirable, the dynamic portion may be compressed, thereby reducing the amount of storage space consumed by the data, and freeing up storage space that can be used by the PSD for OP.

Writing time is shortened even in a memory writing time for each access unit is not constant. A writing time prediction information holding unit holds writing time prediction information for predicting the writing time in a plurality of memory modules for each of a plurality of memory modules. A request selecting unit preferentially selects a write request of which longer writing time is predicted out of a plurality of write requests requiring writing in each of a plurality of memory modules on the basis of the writing time prediction information.

The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of single-level-cell units and a plurality of triple-level cell units. The controller performs a first predetermined number of read processes on a second predetermined number of specific single-level-cell units to program data stored in the second predetermined number of specific single-level-cell units into a specific triple-level cell unit of the triple-level cell units and determines whether any of the second predetermined number of specific single-level-cell units has not been read successfully by any of the read processes when the specific triple-level cell unit cannot be read successfully.