A novel energy-efficient multiplication circuit using analog multipliers and adders reduces the distance data has to move and the number of times the data has to be moved when performing matrix multiplications in the analog domain. The multiplication circuit is tailored to bitwise multiply the innermost product of a rearranged matrix formula to output the generate a matrix multiplication result in form of a current that is then digitized for further processing.

A novel energy-efficient multiplication circuit using analog multipliers and adders reduces the distance data has to move and the number of times the data has to be moved when performing matrix multiplications in the analog domain. The multiplication circuit is tailored to bitwise multiply the innermost product of a rearranged matrix formula to output the generate a matrix multiplication result in form of a current that is then digitized for further processing.

An energy-efficient multiplication circuit uses analog multipliers and adders to reduce the distance that data has to move and the number of times that the data has to be moved when performing matrix multiplications in the analog domain. The multiplication circuit is tailored to bitwise multiply the innermost product of a rearranged matrix formula generate a matrix multiplication result in form of a current that is then digitized for further processing.

An energy-efficient multiplication circuit uses analog multipliers and adders to reduce the distance that data has to move and the number of times that the data has to be moved when performing matrix multiplications in the analog domain. The multiplication circuit is tailored to bitwise multiply the innermost product of a rearranged matrix formula generate a matrix multiplication result in form of a current that is then digitized for further processing.

A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter. The arrangement can be extended to ternary inputs to realize a ternary-binary network (TBN) by adding a circuit to detect 0 input values and adjust the accumulated count accordingly.

Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter. The arrangement can be extended to ternary inputs to realize a ternary-binary network (TBN) by adding a circuit to detect 0 input values and adjust the accumulated count accordingly.

An energy-efficient multiplication circuit uses analog multipliers and adders to reduce the distance that data has to move and the number of times that the data has to be moved when performing matrix multiplications in the analog domain. The multiplication circuit is tailored to bitwise multiply the innermost product of a rearranged matrix formula generate a matrix multiplication result in form of a current that is then digitized for further processing.

An energy-efficient multiplication circuit uses analog multipliers and adders to reduce the distance that data has to move and the number of times that the data has to be moved when performing matrix multiplications in the analog domain. The multiplication circuit is tailored to bitwise multiply the innermost product of a rearranged matrix formula generate a matrix multiplication result in form of a current that is then digitized for further processing.