Disclosed is a semiconductor memory device including a memory cell based on a static random access memory having a 6T or 4T2R configuration and including a first internal node, a second internal node, a first ferroelectric capacitor, and a second ferroelectric capacitor, the first ferroelectric capacitor and the second ferroelectric capacitor having respective first ends connected respectively to the first internal node and the second internal node. For recovering data stored in a non-volatile fashion in the first ferroelectric capacitor and the second ferroelectric capacitor, a first access transistor connected between the first internal node and a first bit line and a second access transistor connected between the second internal node and a second bit line are turned on, and respective capacitive components of the first bit line and the second bit line are used as load capacitances.

An SEU immune flip-flop includes a master stage data latch having an input, an output, a clock input, being transparent in response to a clock signal first state and being latched in response to a clock signal second state, a slave stage data latch having an input coupled to the master stage data latch output, an output, a scan output, a slave latch clock input, a scan slave latch having an input coupled to the slave stage data latch scan output, an output, and a clock input, being transparent in response to the clock signal second state and being latched in response to the clock signal first state. The slave stage data latch includes a switched inverter disabled when the slave latch is in a transparent state and enabled when the slave latch is in a latched state having a time delay longer than an SEU time period.

Apparatus, and methods of operating similar apparatus, might include an array of memory cells and a differential storage device configured to receive information indicative of a data value stored in a particular memory cell of the array of memory cells selected for a programming operation. The differential storage device might include a first non-volatile memory cell connected between a first isolation gate and a voltage node configured to receive a first voltage level, and a second non-volatile memory cell connected between a second isolation gate and the voltage node, and logic responsive to an indication of a loss of power to the apparatus and the information indicative of the data value stored in the particular memory cell to store data to the differential storage device, wherein a gate of the second non-volatile memory cell is connected to a gate of the first non-volatile memory cell.

Embodiments herein describe techniques for a semiconductor device including a SRAM device having multiple SRAM memory cells, and a capacitor coupled to the SRAM device. The capacitor includes a first plate, a second plate, and a capacitor dielectric layer between the first plate and the second plate. The capacitor is to supply power to the multiple SRAM memory cells of the SRAM device in parallel for a period of time. Other embodiments may be described and/or claimed.

An SRAM cell includes two inverters and three transistors. The first inverter includes a first end coupled to a first storage node and a second end coupled to a second storage node. The second inverter includes a first end coupled to the second storage node and a second end coupled to the first storage node. The first transistor includes a first end coupled to the first storage node, a second end and a control end. The second transistor includes a first end coupled to the second end of the first transistor, a second end coupled to a first bit line, and a control end. The third transistor includes a first end coupled between the second end of the first transistor and the first end of the second transistor, a second end, and a control end coupled to the first storage node.

An integrated circuit comprising a field programmable gate array (FPGA) including a plurality of logic tiles wherein each logic tile includes circuitry including (i) logic circuitry and (ii) an interconnect network including a plurality of multiplexers. The FPGA further includes a robust memory cell including: three or more storage elements that are more than one time programmable to store a data state, majority detection circuitry to detect a majority data state stored in the three or more storage elements; and an output, coupled to the majority detection circuitry, to output mode select data which is representative of the majority data state stored in the storage elements. The FPGA also includes mode/function select circuitry to configure a mode of operation of at least a portion of the circuitry in one or more of the plurality of logic tiles based on the mode select data.

A single-event-upset (SEU) stabilized memory cell includes a latch portion including a cross-coupled latch, and at least one cross coupling circuit path in the latch portion including a first series-connected pair of vertical resistors.

Apparatus including an array of volatile memory cells and a differential storage device configured to receive information indicative of a data value stored in a particular memory cell of the array of volatile memory cells and having a first non-volatile memory cell connected between a first isolation gate and a voltage node configured to receive a first voltage level and a second non-volatile memory cell connected between a second isolation gate and the voltage node, wherein a gate of the second non-volatile memory cell is connected to a gate of the first non-volatile memory cell. The apparatus further logic responsive to an indication of a loss of power to the apparatus and the information indicative of the data value stored in the particular memory cell.

The invention introduces a method for verifying memory interface, performed by a processing unit, to include: driving a physical layer of a memory interface to pull-high or pull-low a signal voltage on each Input-Output (IO) pin thereof to a preset level according to a setting; obtaining a verification result corresponding to each IO pin from the memory interface; and storing each verification result in a static random access memory (SRAM), thereby enabling a testing host to obtain each verification result of the SRAM through a test interface. The testing host may examine each verification result to know whether any unexpected error has occurred in signals on the IO pins of the memory interface.

A memory device capable of reading reference data while achieving optimization of electric power consumption is provided. A memory device includes a memory area storing reference data of N (1) dimensions each composed of M (1) bits. A number of memory grains each composed of nonvolatile memory and power drivers paired with the memory grains to supply electrical power to the memory grains are provided in each region specified by column lines in the number and M row lines, the number being one to N inclusive. When the power driver receives a control signal from the corresponding one of the column lines, a control signal from the corresponding one of the M row lines, and a clock signal, the power driver supplies electrical power to the memory grain in synchronization with the clock signal.