A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold voltage being below a predetermined detection voltage threshold following an erase operation. The control means is also configured to selectively apply at least one programming pulse of a maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold.

An erasing method used in a flash memory comprising at least one memory block divided into a plurality of memory sectors is illustrated. Whether the memory block or the memory sector corresponding to an address has at least one under-erased transistor memory cell according to a sector enable signal is verified, wherein the sector enable signal is determined according to whether the memory block has at least one over-erased transistor memory cell. The transistor memory cells of the memory block or the memory sector will be erased according to the sector enable signal if the memory block or the memory sector corresponding to the address has the under-erased transistor memory cell.

Systems, apparatuses and methods may provide for identifying a target sub-block of NAND strings to be partially or wholly erased in memory and triggering a leakage current condition in one or more target select gate drain-side (SGD) devices associated with the target sub-block. Additionally, the leakage current condition may be inhibited in one or more remaining SGD devices associated with remaining sub-blocks of NAND strings in the memory. In one example, triggering the leakage current condition in the one or more target SGD devices includes setting a gate voltage of the one or more target SGD devices to a value that generates a reverse voltage that exceeds a threshold corresponding to the leakage current condition.

An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.

This invention introduces a flash memory device and a method which are capable of quickly recovering the over-erased memory cells while preventing adverse influence to normal cells that are not over-erased. The flash memory device comprises a memory array and a memory controller coupled to the memory array. The memory controller is configured to select a memory block which comprises at least one over-erased memory cell. The memory controller is further configured to apply a negative voltage to the common bulk line and the common source line of the selected memory block. The memory controller is further configured apply a positive voltage to word lines that are coupled to the at least one over-erased memory cell in the selected memory block, and apply the positive voltage to word lines that are not coupled to any one of the at least one over-erased memory cell in the selected memory block.

A memory storage device including a flash memory and a controller circuit is provided. The flash memory includes a plurality of memory cells. Each of the memory cells includes a substrate, a drain terminal, a source terminal, and a gate terminal. The controller circuit is coupled to the flash memory. The controller circuit is configured to perform a first erase operation on the memory cells to obtain a first erase threshold voltage distribution, and perform a program operation on the memory cells to obtain a program threshold voltage distribution. The first erase threshold voltage distribution is larger than a first target voltage. The program threshold voltage distribution is smaller than a second target voltage. The first target voltage is larger than the second target voltage. A writing method of a flash memory is also provided.

An erasing method of a memory device includes the following steps. It is determined whether a memory passes the first erasing verification operation according to the first erasing verification threshold. When the memory does not pass the first erasing verification operation, an erasing operation is performed on the memory. When the memory passes the first erasing verification operation, a flag is generated and it is determined whether the memory passes a second erasing verification operation according to the second erasing verification threshold. When the memory does not pass the second erasing verification operation, the erasing operation is performed on the memory. When the memory passes the second erasing verification operation, an over-erase correction is performed on the memory. It is determined whether there is a flag indicating that all addresses pass the first erasing verification to determine whether the memory passes the first or second erasing verification operation.

A memory device includes a memory array comprising memory cells and control logic. The control logic performs operations including: causing a first erase pulse to be applied to a memory line of the memory array to perform an erase operation, the memory line being a conductive line coupled to a string of the memory cells; suspending the erase operation in response to receipt of a suspend command during a ramping period of the first erase pulse; recording a suspend voltage level of the first erase pulse when suspended; causing the erase operation to be resumed in response to an erase resume command; selectively modifying a pulse width of a flattop period of a second erase pulse based on the suspend voltage level; and causing the second erase pulse to be applied to the memory line during a resume of the erase operation.

An erasing method of a single-gate non-volatile memory is provided. The single-gate non-volatile memory has a single floating gate. The erasing method includes applying a voltage to the drain without applying to the gate to create and control an inversion layer. Therefore the required erasing voltage is reduced and the erasing speed is improved to avoid the over-erase problem.

When a control circuit has received a first erase command, the control circuit controls performing a first pre-write process to allow a first storage device and a second storage device to have threshold voltages, respectively, both increased, and the control circuit thereafter controls performing an erase process to allow the first storage device and the second storage device to have their respective threshold voltages both decreased to be smaller than a prescribed erase verify level. When the control circuit has received a second erase command, the control circuit controls performing a second pre-write process to allow one of the first storage device and the second storage device to have its threshold voltage increased, and control circuit subsequently controls performing the erase process.