The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines for selecting a row according to a particular address given on the address input lines. Additional address mask input lines are provided, each address mask input line being assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line. The method for testing said electronic memory device is performed with a significant lower number of read/write operations, since by ignoring a particular address line a plurality of write operations can be performed simultaneously.

The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines for selecting a row according to a particular address given on the address input lines. Additional address mask input lines are provided, each address mask input line being assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line. The method for testing said electronic memory device is performed with a significant lower number of read/write operations, since by ignoring a particular address line a plurality of write operations can be performed simultaneously.

A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.

A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.

A memory device includes a controller, a multiplexer, a deserializer, a data modifier, a memory cell array and an error detector. The controller is configured to generate signals in response to an address signal and a command signal. The multiplexer is configured to output a clock signal as internal data signals when the test mode signal is activated. The deserializer is configured to deserialize N bit values included in the internal data signals to generate deserialized signals. The data modifier is configured to invert the deserialized signals to generate bit line signals in response to an inversion control signal and the data modifying signals. The memory cell array is configured to store the bit line signals to memory cells corresponding to the address signal. The error detector is configured to determine if an error exists in signals read from the memory cells and to output an error detecting signal.

When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed. An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.

A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.

A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.

When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed. An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.

When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed. An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.