An interposer for inspecting reliability of a semiconductor chip is disclosed. The interposer for inspection includes: at least one active pad disposed in an active region of a first surface, and including: pads through which data and a control signal for testing an inspection target chip are received (input) and sent (output) during an active mode; and pads for receiving a power-supply voltage needed to operate the inspection target chip and the interposer during the active mode; at least one passive pad disposed in a passive region of the first surface, and including: pads receiving data for testing the inspection target chip during a passive mode, and a power-supply voltage needed to operate the inspection target chip and the interposer during the passive mode; and at least one bump pad disposed over a second surface facing the first surface, and to be coupled to the inspection target chip.

According to the present invention, a semiconductor inspection device includes a control section that outputs a signal to inspect a semiconductor wafer, a contact section comprising contact terminals connected to the control section, a probe card that can simultaneously contact a plurality of semiconductor chips formed on the semiconductor wafer and a drive section, wherein the contact terminals can contact some of electrode pads provided for the probe card and the drive section drives the contact section so as to switch electrode pads in contact with the contact terminals.

An electrically connecting assembly has a probe card and a conductive rubber sheet. The probe card has multiple probes. Each of the probes has a first contact end and an inclined guiding segment inclined to a same direction. The conductive rubber sheet is mounted on the probe card, is located in a side of the probe card having the inclined guiding segment, and has a rubber sheet body and multiple wires distributed in the rubber sheet body. The first contact end of each of the probes is capable of contacting a group of the wires. The inclined guiding segment of each of the probes is capable of guiding a direction for the group of the wires to be squeezed and deformed. The electrically connecting assembly prevents the probes from directly abutting the test object to reduce the replacement frequency.

Space transformers, planarization layers for space transformers, methods of fabricating space transformers, and methods of planarizing space transformers are disclosed herein. In one embodiment, the space transformers include a space transformer assembly including a first rigid space transformer layer, a second rigid space transformer layer, and an attachment layer that extends between the first rigid space transformer layer and the second rigid space transformer layer. In another embodiment, the space transformers include a space transformer body and a flex cable assembly. The planarization layer includes an interposer, a resilient dielectric layer, a planarized rigid dielectric layer, a plurality of holes, and an electrically conductive paste extending within the plurality of holes. In one embodiment, the methods include methods of fabricating the space transformer assembly. In another embodiment, the methods include methods of planarizing a space transformer.

Aspects of the invention include a wafer test device with a conformal laminate and rigid probes extending from the laminate to form an electrical connection with a microcircuit under test. The wafer test device also includes a spring plate on a side of the laminate that is opposite a side from which the rigid probes extend. The spring plate includes a conformal inner frame and a rigid outer frame. The laminate is attached to the inner frame of the spring plate.

A testing apparatus comprises a test interface board comprising a plurality of socket interface boards, wherein each socket interface board comprises: a) an open socket to hold a DUT; b) a discrete active thermal interposer comprising thermal properties and operable to make thermal contact with the DUT; c) a superstructure operable to contain the discrete active thermal interposer; and d) an actuation mechanism operable to provide a contact force to bring the discrete active thermal interposer in contact with the DUT.

A stack type test interface board assembly is provided herein, which comprises: a space transform board having a narrow pitch transform board and a wide pitch transform board, a plurality of first connection nodes disposed on a side of the narrow pitch transform board to be electrically connected to a finished or semi-finished semiconductor product, a plurality of second connection nodes disposed on a side of the wide pitch transform board, and a printed circuit board where a side thereof is electrically connected to the plurality of the second connection nodes. The narrow pitch transform board and the wide pitch transform board are assembled in perpendicular stack into the space transform board. A pitch between each two of the plurality of the first connection nodes is smaller than a pitch between each two of the plurality of the second connection nodes.

Proposed are an anodic aluminum oxide mold capable of manufacturing a molded article having at least a portion with a dimensional range of several tens of μm, and a mold structure including the same. Additionally, proposed are a method of manufacturing a molded article with a dimensional range of several tens of μm using the anodic aluminum oxide mold, and a molded article manufactured thereby.

A probe unit according to the present invention is suitable for allowing a large current to flow. In the probe unit that accommodates a plurality of contact probes for electrically connecting an inspection target object and a signal processing device used to output an inspection signal, both ends of a large current probe (3) are electrically connected to electrodes of a contact target object, and a large current is made to flow via a metal block (50) that comes into contact with both end portions of the large current probe (3).

A printed circuit board (PCB) test fixture includes a substrate, a first insulation layer formed on the substrate, a conductor layer formed on the first insulation layer and electrically connected to the upper electrodes through at least one first connection member, a second insulation layer formed on the first insulation layer, and multiple conductive cones arranged on the second insulation layer in a matrix form. A part of the conductive cones is electrically connected to the conductor layer through at least one second connection member. The circuit layout of the conductor layer, the at least one first connection member and the at least one second connection member is employed to supply testing power to a part of the conductive cones and an adjustable arrangement of the conductive cones to enhance density of test probes upon electrical testing.