A diagnostic system for a power supply having first and second output terminals that output first and second reference voltages, respectively, is provided. The diagnostic system includes a microcontroller having an analog-to-digital converter with first and second banks of channels. The microcontroller samples the first reference voltage at a first sampling rate utilizing a first common channel in the first bank of channels to obtain a first predetermined number of voltage samples. The microcontroller determines a first number of voltage samples in the first predetermined number of voltage samples in which the first reference voltage was outside of a predetermined voltage range. The microcontroller sets a first power supply diagnostic flag equal to a first fault value if the first number of voltage samples is greater than a first threshold number of voltage samples.

Shielded probe systems are disclosed herein. The shielded probe systems are configured to test a device under test (DUT) and include an enclosure that defines an enclosure volume, a translation stage with a stage surface, a substrate-supporting stack extending from the stage surface, an electrically conductive shielding structure, an isolation structure, and a thermal shielding structure. The substrate-supporting stack includes an electrically conductive support surface and a temperature-controlled chuck. The electrically conductive shielding structure defines a shielded volume. The isolation structure electrically isolates the electrically conductive shielding structure from the enclosure and from the translation stage. The thermal shielding structure extends within the enclosure volume and at least partially between the enclosure and the substrate-supporting stack.

A repairable rigid test probe system includes an annular gimbal supported by an annular gimbal bearing of a probe card assembly, a test substrate seated and aligned within the annular gimbal, a rigid die including thick periphery and a thin center containing an array of through holes that is aligned above the test substrate, and an array of rigid probes inserted into each of the array of through holes, where each rigid probe includes: a tail end that contacts a connection on a facing surface of the test substrate, a collar limiting a distance of insertion, and a tip that contacts a corresponding contact on a facing surface of a device under test.

Proposed are a probe card for performing a circuit test of a wafer and a manufacturing method therefor. More particularly, proposed are a probe card and a manufacturing method therefor, in which the process of inserting probe pins is eliminated.

The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application. In each embodiment, however, the critical improvement of this disclosure is the location of the passive components used for supply filtering/decoupling relative to prior art. All three embodiments require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.

The embodiments of the present invention relate to semiconductor device manufacturing, and more particularly to structures and methods of directly testing semiconductor wafers having micro-solder connections. According to one embodiment of the present invention, a method of forming a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer, is disclosed. According to another embodiment, a method of testing the pattern of micro-solder connections is disclosed. According to another embodiment, a novel electrical probe tip structure, having contacts on the same pitch as the pattern of micro-solder connections is disclosed.

An adapter for testing electrical equipment can include a first receptacle end having at least one first coupling feature, where the at least one first coupling feature is configured to couple to a power source and a first electrical device, where the first receptacle end is configured to receive from the power source at least one first test signal and send the at least one first test signal to the first electrical device. The adapter can also include a sensing device configured to receive at least one first response signal from the first electrical device, where the at least one first response signal is in response to and based on the first electrical device receiving the at least one first test signal.

A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

A wafer inspection method whereby inspection accuracy and operation efficiency is improved. A method for performing electrical inspection by bringing, at one time, a plurality of probes into contact with a plurality of pads in chips on a wafer. A chuck step S1 for heating the wafer to an inspection temperature; a first position recognition step S2 for recognizing all the positions of the pads of the chips; a second position recognition step S3 for re-recognizing, before performing the electrical inspection, the position of the pads for the purpose of recognizing the positional shifts of the pads due to thermal expansion when the wafer chuck is heated; and a correction step S4 for correcting contact positions with respect to the probes, the contact positions being corrected on the basis of pad positions, which have been re-recognized in the second position recognition step S3 on the basis of the pad positions recognized in the first position recognition step S2, and which have been updated.

An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.