An array board 11b includes a display section AA, a source line 20 connected to the display section AA, a test circuit 40 connected to the source line 20 and configured to test the display section AA, a panel-side image input terminal that is disposed such that the test circuit 40 is between the terminal and the display section AA and to which a signal to be supplied to the source line 20 is input, a terminal connection line 51 connecting the source line 20 to the pane-side image input terminal 35A and the terminal connection line 51 including the terminal connection line 51 at least a part of which overlaps the test circuit 40 and a flattening film (insulation film) 28 at least disposed between an overlapping portion of the test circuit 40 and the terminal connection line 51.

An array substrate includes a substrate, a first metal layer disposed on the substrate, an insulating layer disposed on the first metal layer, and a second metal layer disposed on the insulating layer. The substrate includes a low-voltage area. One of the first metal layer and the second metal layer includes a plurality of low-voltage signal lines in the low-voltage area. The other one of the first metal layer and the second metal layer includes one or more third auxiliary traces in the low-voltage area. The insulating layer is provided with a plurality of pairs of conductive metalized holes. Each pair of the conductive metalized holes includes two conductive metalized holes electrically connecting two ends of a corresponding third auxiliary trace and two ends of a corresponding low-voltage signal line.

A thin film transistor array substrate, a manufacturing method thereof and a display device are provided, and the thin film transistor array substrate includes: a base substrate, a gate electrode disposed on the base substrate, a gate insulating layer and an active layer which are disposed on the gate electrode sequentially, and a pixel electrode, a common electrode, and a transparent electrode layer which are disposed on the base substrate, the transparent electrode layer and the pixel electrode or the common electrode are prepared in a same layer and by a same material; the transparent electrode layer is disposed under the gate insulating layer, an orthogonal projection of the active layer on the base substrate is located within a region of an orthogonal projection of the transparent electrode layer.

An array substrate, a display panel, a display device, and a method for fabricating an array substrate are provided. The array substrate comprises gate lines and data lines on a substrate plate which are insulated from each other and intersect to define sub-pixel units, and the data lines comprise a first data line and a second data line which are arranged side by side between two neighboring columns of sub-pixel units. Between two of the sub-pixel units which are neighbors in a column direction, at least a portion of the first data line is arranged in a layer different from the neighboring second data line. At least a part of the first data line is arranged in a layer different from that of the neighboring second data line, to overcome the problem of short circuit between dual data lines.

A display may have an array of pixels arranged in rows and columns. Display driver circuitry may be provided along an edge of the display. Data lines that are associated with columns of the pixels may be used to distribute data from the display driver circuitry to the pixels. Gate lines in the display may each have a horizontal straight portion that extends along a respective row of the pixels and may each have one or more non-horizontal segments such as zigzag segments. The non-horizontal portion of each gate line may be connected to the horizontal straight portion of the gate line by a via. The non-horizontal portions may each have portions that are overlapped by portions of the data lines. Dummy gate line structures may be provided on the display that are not coupled to any of the pixels in the display.

Display backplanes and pixel element structures are described. In an embodiment, a pixel electrode is located between two stacked data lines, with a left edge of the pixel electrode being separated from a first lower data line by approximately a same distance as a right edge of the pixel electrode is separated from a second lower data line.

A display panel is provided. At least two first wires in a second direction are electrically connected to each other and at least two second wires in the second direction are electrically connected to each other. The space in the second direction is fully used to arrange the first wires and the second wires to ensure the number of first via holes disposed corresponding to the first wires and the number of second via holes disposed corresponding to the second wire, thereby ensuring the connectivity of a transparent conductive block that bridges the first wires and the second wires through the first via holes and the second via holes.

An array substrate, a display device and a method for fabrication the array substrate are provided. The array substrate comprises a base substrate; gate lines and data lines; pixel electrodes; a common electrode layer including at least one first slot and at least one second slot at least partially overlapped with the first slot; at least one shielding electrode disposed above the data line; and at least one shielding branch electrode disposed above the gate line and electrically connected to the shielding electrode. A projection of the shielding electrode onto the data line is at least partially overlapped with the data line, a projection of the shielding branch electrode onto the gate line is at least partially overlapped with the gate line, and the array substrate exhibits at least one raised area where the at least one shielding branch electrode is embedded.

The present disclosure provides a display substrate, including: a wiring mounting region. The wiring mounting region includes first wires and second wires, each of the first wires intersecting with one or more of the second wires, thereby defining one or more intersectional regions; and a semiconductor pattern between the first wire and the one or more second wires, the semiconductor pattern having at least one cross-sectional width covering at least a portion of at least one of the intersectional regions.

A liquid crystal display device includes a first substrate spaced from a second substrate, a liquid crystal layer between the first and second substrates, a gate line, a data line, a first sub-pixel electrode, and a second sub-pixel electrode on the first substrate. The display device also includes a first switch and a second switch. The first switch is connected to the gate line, the data line, and the first sub-pixel electrode. The second switch is connected to the gate line, the data line, and the second sub-pixel electrode. The second switch includes a first gate electrode connected to the gate line and a second gate electrode not connected to the gate line.