Patent classifications
H01G4/30
GALVANIC HIGH VOLTAGE ISOLATION CAPABILITY ENHANCEMENT ON REINFORCED ISOLATION TECHNOLOGIES
A microelectronic device includes a semiconductor substrate and a high voltage isolation capacitor over the substrate. The capacitor includes a bottom capacitor plate over the substrate. Dielectric layers are formed above the bottom capacitor plate, including a top dielectric layer. A high dielectric layer on the top dielectric layer includes at least a first sublayer having a first dielectric constant that is higher than a dielectric constant of the top dielectric layer. A top capacitor plate is formed on the high dielectric layer over the bottom capacitor plate. An electric field abatement structure surrounds the top capacitor plate. The electric field abatement structure includes a shelf of the high dielectric layer extending outward from a lower corner of the bottom capacitor plate at least 14 microns, and an isolation break in the high dielectric layer past the shelf, in which the first sublayer is removed from the isolation break.
GALVANIC HIGH VOLTAGE ISOLATION CAPABILITY ENHANCEMENT ON REINFORCED ISOLATION TECHNOLOGIES
A microelectronic device includes a semiconductor substrate and a high voltage isolation capacitor over the substrate. The capacitor includes a bottom capacitor plate over the substrate. Dielectric layers are formed above the bottom capacitor plate, including a top dielectric layer. A high dielectric layer on the top dielectric layer includes at least a first sublayer having a first dielectric constant that is higher than a dielectric constant of the top dielectric layer. A top capacitor plate is formed on the high dielectric layer over the bottom capacitor plate. An electric field abatement structure surrounds the top capacitor plate. The electric field abatement structure includes a shelf of the high dielectric layer extending outward from a lower corner of the bottom capacitor plate at least 14 microns, and an isolation break in the high dielectric layer past the shelf, in which the first sublayer is removed from the isolation break.
Ceramic electronic component and method of manufacturing the same
A ceramic electronic component includes a multilayer chip having a substantially rectangular parallelepiped shape and including dielectric layers and internal electrode layers that are alternately stacked, the internal electrode layers being alternately exposed to two edge faces of the multilayer chip facing each other, and a pair of external electrodes respectively formed on the two edge faces so as to be connected to the internal electrode layers exposed on the respective edge faces, each external electrode extending to at least one side face of the multilayer chip, wherein in the multilayer chip, oxides including Zn and Ni are present around the internal electrode layer in a vicinity of a connection part connecting the internal electrode layer to the external electrode.
Ceramic electronic component and method of manufacturing the same
A ceramic electronic component includes a multilayer chip having a substantially rectangular parallelepiped shape and including dielectric layers and internal electrode layers that are alternately stacked, the internal electrode layers being alternately exposed to two edge faces of the multilayer chip facing each other, and a pair of external electrodes respectively formed on the two edge faces so as to be connected to the internal electrode layers exposed on the respective edge faces, each external electrode extending to at least one side face of the multilayer chip, wherein in the multilayer chip, oxides including Zn and Ni are present around the internal electrode layer in a vicinity of a connection part connecting the internal electrode layer to the external electrode.
Leadless stack comprising ceramic capacitor
The present invention provides a leadless stacked ceramic capacitor. the capacitor body are respectively provided with internal electrode terminals. The part forms an electrical connection with the external electrodes, and a plurality of multilayer ceramic capacitors are vertically stacked, and the two adjacent external electrodes are cured to form an adhesive interface by polymer conductive adhesive, and the polymer conductive adhesive includes 75%˜85% metal powder and 15%˜25% viscose provide support strength and conductive channels.
Leadless stack comprising ceramic capacitor
The present invention provides a leadless stacked ceramic capacitor. the capacitor body are respectively provided with internal electrode terminals. The part forms an electrical connection with the external electrodes, and a plurality of multilayer ceramic capacitors are vertically stacked, and the two adjacent external electrodes are cured to form an adhesive interface by polymer conductive adhesive, and the polymer conductive adhesive includes 75%˜85% metal powder and 15%˜25% viscose provide support strength and conductive channels.
Multi-layered ceramic capacitor and method of manufacturing the same
A multilayer ceramic capacitor includes a ceramic body including a dielectric layer and first and second internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween, and first and second external electrodes disposed outside of the ceramic body and connected to the first and second internal electrodes, respectively. The ceramic body includes an active portion including of the first and second internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween to form capacitance, and a cover portion disposed in upper and lower portions of the active portion. The cover portion has a larger number of pores than the dielectric layer of the active portion, and the cover portion includes a ceramic-polymer composite filled with a polymer in the pores of the cover portion.
Multi-layered ceramic capacitor and method of manufacturing the same
A multilayer ceramic capacitor includes a ceramic body including a dielectric layer and first and second internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween, and first and second external electrodes disposed outside of the ceramic body and connected to the first and second internal electrodes, respectively. The ceramic body includes an active portion including of the first and second internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween to form capacitance, and a cover portion disposed in upper and lower portions of the active portion. The cover portion has a larger number of pores than the dielectric layer of the active portion, and the cover portion includes a ceramic-polymer composite filled with a polymer in the pores of the cover portion.
Ceramic electronic component comprising dielectric grains having a core-dual shell structure and method of manufacturing the same
A ceramic electronic component includes a body, including a dielectric layer and an internal electrode. The dielectric layer includes a plurality of dielectric grains, and at least one of the plurality of dielectric grains has a core-dual shell structure having a core and a dual shell. The dual shell includes a first shell, surrounding at least a portion of the core, and a second shell, surrounding at least a portion of the first shell. The dual shell includes different types of rare earth elements R1 and R2, and R2.sub.S1/R1.sub.S1 is 0.01 or less and R2.sub.S2/R1.sub.S1 is 0.5 to 3.0, where R1.sub.S1 and R1.sub.S2 denote concentrations of R1 included in the first shell and the second shell, respectively, and R2.sub.S1 and R2.sub.S2 denote concentrations of R2 included in the first shell and the second shell, respectively.
Ceramic electronic component comprising dielectric grains having a core-dual shell structure and method of manufacturing the same
A ceramic electronic component includes a body, including a dielectric layer and an internal electrode. The dielectric layer includes a plurality of dielectric grains, and at least one of the plurality of dielectric grains has a core-dual shell structure having a core and a dual shell. The dual shell includes a first shell, surrounding at least a portion of the core, and a second shell, surrounding at least a portion of the first shell. The dual shell includes different types of rare earth elements R1 and R2, and R2.sub.S1/R1.sub.S1 is 0.01 or less and R2.sub.S2/R1.sub.S1 is 0.5 to 3.0, where R1.sub.S1 and R1.sub.S2 denote concentrations of R1 included in the first shell and the second shell, respectively, and R2.sub.S1 and R2.sub.S2 denote concentrations of R2 included in the first shell and the second shell, respectively.