A semiconductor device includes a semiconductor layered structure, an electrode unit, and an anti-adsorption layer. The electrode unit is disposed on an electrode connecting region of the semiconductor layered structure. The anti-adsorption layer is disposed on a top surface of the electrode unit opposite to the semiconductor layered structure and is electrically connected to the electrode unit. The anti-adsorption layer has an adsorption capacity for at least one of gaseous contaminants and particulate contaminants which is lower than that of the electrode unit. Also disclosed herein is a light-emitting system including the semiconductor device.

A semiconductor device includes a semiconductor layered structure, an electrode unit, and an anti-adsorption layer. The electrode unit is disposed on an electrode connecting region of the semiconductor layered structure. The anti-adsorption layer is disposed on a top surface of the electrode unit opposite to the semiconductor layered structure and is electrically connected to the electrode unit. The anti-adsorption layer has an adsorption capacity for at least one of gaseous contaminants and particulate contaminants which is lower than that of the electrode unit. Also disclosed herein is a light-emitting system including the semiconductor device.

The invention relates to a method for producing a light-emitting diode, comprising a stack formed of a first semiconductor layer 11 and of an active layer 13, a reflective electrode 4 extending in contact with the first semiconductor layer 11, comprising a step of determining a distance between emitting dipoles that are located in the active layer 13 and the reflective electrode 4 for which a lifetime of the emitting dipoles having a chosen orientation is longer than that of the emitting dipoles having the non-chosen orientation.

A method of manufacturing a semiconductor light-emitting device, comprises the steps of providing a first substrate; providing multiple epitaxial units on the first substrate, wherein the plurality of epitaxial units comprises: multiple first epitaxial units, wherein each of the first epitaxial units has a first geometric shape and a first area; and multiple second epitaxial units, wherein each of the second epitaxial units has a second geometric shape and a second area; providing a second substrate with a surface; transferring the multiple second epitaxial units to the surface of the second substrate; and dividing the first substrate to form multiple first semiconductor light-emitting devices, wherein each of the first semiconductor light-emitting devices has the first epitaxial unit; wherein the first geometric shape is different from the second geometric shape, or the first area is different from the second area.

A multilayer structure including a hexagonal epitaxial layer, such as GaN or other group III-nitride (III-N) semiconductors, a <111> oriented textured layer, and a non-single crystal substrate, and methods for making the same. The textured layer has a crystalline alignment preferably formed by the ion-beam assisted deposition (IBAD) texturing process and can be biaxially aligned. The in-plane crystalline texture of the textured layer is sufficiently low to allow growth of high quality hexagonal material, but can still be significantly greater than the required in-plane crystalline texture of the hexagonal material. The IBAD process enables low-cost, large-area, flexible metal foil substrates to be used as potential alternatives to single-crystal sapphire and silicon for manufacture of electronic devices, enabling scaled-up roll-to-roll, sheet-to-sheet, or similar fabrication processes to be used. The user is able to choose a substrate for its mechanical and thermal properties, such as how well its coefficient of thermal expansion matches that of the hexagonal epitaxial layer, while choosing a textured layer that more closely lattice matches that layer.

A multilayer structure including a hexagonal epitaxial layer, such as GaN or other group III-nitride (III-N) semiconductors, a <111> oriented textured layer, and a non-single crystal substrate, and methods for making the same. The textured layer has a crystalline alignment preferably formed by the ion-beam assisted deposition (IBAD) texturing process and can be biaxially aligned. The in-plane crystalline texture of the textured layer is sufficiently low to allow growth of high quality hexagonal material, but can still be significantly greater than the required in-plane crystalline texture of the hexagonal material. The IBAD process enables low-cost, large-area, flexible metal foil substrates to be used as potential alternatives to single-crystal sapphire and silicon for manufacture of electronic devices, enabling scaled-up roll-to-roll, sheet-to-sheet, or similar fabrication processes to be used. The user is able to choose a substrate for its mechanical and thermal properties, such as how well its coefficient of thermal expansion matches that of the hexagonal epitaxial layer, while choosing a textured layer that more closely lattice matches that layer.

A light emitting device according to an embodiment includes a substrate; first to Mth light emitting cells (where M is a positive integer of two or more) which are arranged on the substrate so as to be spaced apart from each other; and first to (M−1)th interconnection wires which electrically connect the first to Mth light emitting cells in series, wherein an mth light emitting cell (where 1≦m≦M) includes a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer, which are sequentially arranged on the substrate, and wherein an nth interconnection wire (where 1≦n≦M−1) interconnects the first conductive type semiconductor of the nth light emitting cell with the second conductive type semiconductor of the (n+1)th light emitting cell, and has a plurality of first branch wires which are spaced apart from each other.

A light emitting device according to an embodiment includes a substrate; first to Mth light emitting cells (where M is a positive integer of two or more) which are arranged on the substrate so as to be spaced apart from each other; and first to (M−1)th interconnection wires which electrically connect the first to Mth light emitting cells in series, wherein an mth light emitting cell (where 1≦m≦M) includes a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer, which are sequentially arranged on the substrate, and wherein an nth interconnection wire (where 1≦n≦M−1) interconnects the first conductive type semiconductor of the nth light emitting cell with the second conductive type semiconductor of the (n+1)th light emitting cell, and has a plurality of first branch wires which are spaced apart from each other.

Disclosed is a light-emitting diode with an n-type graded buffer layer and a manufacturing method therefor. An epitaxial structure of a light-emitting diode comprises: a growth substrate; an n-type graded buffer layer located on the growth substrate; an n-type limiting layer (231) located on the n-type graded buffer layer; an active layer (232) located on the n-type limiting layer (231); and a p-type limiting layer (233) located on the active layer (232). A buffer layer is converted into an n-type graded buffer layer by means of an ion implantation method, and is applied to a light-emitting diode chip of a vertical structure while ensuring that a high-quality epitaxial structure is obtained, thereby being able to effectively reduce the contact resistance.

In an embodiment, a component includes a carrier and a main body disposed on the carrier, wherein the main body includes a first semiconductor layer of a first charge carrier type, a second semiconductor layer of a second charge carrier type, and an optically active zone located therebetween, the optically active zone configured to emit radiation, wherein the first semiconductor layer includes a contiguous main layer and local regions at least locally buried in the main layer and laterally enclosed by the main layer, wherein the local regions are doped, and wherein the local regions has a smaller vertical layer thickness compared to the first semiconductor layer.