Provided is a semiconductor device including: a first external electrode which includes a circular outer peripheral portion; a MOSFET chip; a control circuit chip which receives voltages of a drain electrode and a source electrode of the MOSFET and supplies a signal to a gate electrode to control the MOSFET on the basis of the voltage; a second external electrode which is disposed on an opposite side of the first external electrode with respect to the MOSFET chip and includes an external terminal on a center axis of the circular outer peripheral portion of the first external electrode; and an isolation substrate which isolates the control circuit chip from the external electrode. The first external electrode, the drain electrode and the source electrode of the MOSFET chip, and the second external electrode are disposed to be overlapped in a direction of the center axis. The drain electrode of the MOSFET chip and the first external electrode are connected. The source electrode of the MOSFET chip and the second external electrode are connected.

A method of positioning a component arranged on a substrate includes providing a substrate having at least one device for sensing an electromagnetic field arranged thereat, generating a dedicated conductive-trace structure on the substrate, the dedicated conductive-trace structure being provided for the purpose of generating an electromagnetic field having a known field distribution, applying an electric voltage to the dedicated conductive-trace structure, so that the dedicated conductive-trace structure generates the electromagnetic field having the known field distribution, and sensing the generated electromagnetic field having the known field distribution by means of the device for sensing an electromagnetic field. According to the method, the location of the component in relation to the substrate is determined on the basis of the above-mentioned sensing of the electromagnetic field having the known field distribution.

A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.

Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer.

A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.

In an embodiment an optoelectronic semiconductor device includes a semiconductor chip having a semiconductor layer sequence with an active region, a radiation exit surface arranged parallel to the active region and a plurality of side faces arranged obliquely or perpendicular to the radiation exit surface. The device further includes a contact track electrically connecting the semiconductor chip to a contact surface configured to externally contact the semiconductor device, a molding and a rear side of the semiconductor chip remote from the radiation exit surface, the rear side being free of a material of the molding, wherein one of the side faces is configured as a mounting side face for fastening of the semiconductor device, and wherein the contact track partially runs on one of the side faces.

A semiconductor device includes a carrier, a power semiconductor die that includes first and second opposite facing main surfaces, a side surface extending from the first main surface to the second main surface, and first and second electrodes disposed on the first and second main surfaces, respectively, a die attach material arranged between the carrier and the first electrode, wherein the die attach material forms a fillet at the side surface of the power semiconductor die, wherein a fillet height of the fillet is less than about 95% of a height of the power semiconductor die, wherein the height of the power semiconductor die is a length of the side surface, and wherein a maximum extension of the die attach material over edges of a main surface of the power semiconductor die facing the die attach material is less than about 200 micrometers.

A rectifying device includes a semiconductor die having first and second opposing surfaces and a first terminal and a second terminal. A power transistor has a source terminal connected to one of the first terminal or the second terminal of the rectifying device. A drain terminal is connected to the other one of the first terminal or the second terminal of the rectifying device and a gate. A gate control circuit is operable to control a gate voltage at the gate of the power transistor based on at least one parameter relating to at least one of a voltage and a current between the first terminal and the second terminal. A capacitor structure is provided wherein the power transistor, the gate control circuit and the capacitor structure are arranged in the semiconductor die forming a monolithic structure and the first and second opposing surfaces are at least in part metallised.

A semiconductor device including: a semiconductor chip; a plurality of insulating substrates mounted with the semiconductor chip; a printed circuit board facing the plurality of insulating substrates; and a conductive member for electrically connecting the plurality of insulating substrates and the printed circuit board is provided. The printed circuit board has a first through part arranged between the plurality of insulating substrates being adjacent to each other in a top view, and a second through part different from the first through part in shape in the top view.

A power semiconductor device includes a planar rectifying element, a base electrode, a first solder layer, a lead electrode, a second solder layer, and first and second sealing portions. The base electrode is electrically connected to the rectifying element via the first solder layer formed on a first surface of the rectifying element. The lead electrode is electrically connected to the rectifying element via the second solder layer formed on a second surface of the rectifying element. The first sealing portion is formed of a first resin and provided in a recess; the recess is formed by the first surface of the rectifying element and the first solder layer or by the second surface of the rectifying element and the second solder layer. The second sealing portion is formed of a second resin and separately from the first sealing portion to cover an outer surface of the first sealing portion.