H01L2224/90

PACKAGE STRUCTURES AND METHODS OF MANUFACTURING THE SAME

Package structures and methods of forming the same are disclosed. The package structure includes a package, a device and a screw. The package includes a plurality of dies, an encapsulant encapsulating the plurality of dies, and a redistribution structure over the plurality of dies and the encapsulant. The device is disposed over the package, wherein the dies and the encapsulant are disposed between the device and the redistribution structure. The screw penetrates through the package and the device.

PACKAGE STRUCTURES AND METHODS OF MANUFACTURING THE SAME

Package structures and methods of forming the same are disclosed. The package structure includes a package, a device and a screw. The package includes a plurality of dies, an encapsulant encapsulating the plurality of dies, and a redistribution structure over the plurality of dies and the encapsulant. The device is disposed over the package, wherein the dies and the encapsulant are disposed between the device and the redistribution structure. The screw penetrates through the package and the device.

Semiconductor apparatus

According to the present invention, a semiconductor apparatus includes a semiconductor device, a case surrounding the semiconductor device, a spring terminal including a first connection portion extending to a top surface of the case, and a second connection portion provided on the top surface of the case and a control substrate provided on the second connection portion, wherein the first connection portion is connected to the semiconductor device, the second connection portion includes a first end connected to an end of the first connection portion, and a second end opposite to the first end, the second connection portion being a flat plate and having an elastic force using the first end as a supporting point, the second end contacts the control substrate with an elastic force, and the second connection portion has a constriction structure having a notch formed in a side surface along a longitudinal direction.

VERTICAL CHIP INTERPOSER AND METHOD OF MAKING A CHIP ASSEMBLY CONTAINING THE VERTICAL CHIP INTERPOSER
20190252361 · 2019-08-15 ·

A multi-grooved interposer includes an interposer substrate containing multiple parallel grooves laterally extending along a first direction and laterally spaced among one another along a second direction, and multiple conductive strips. The multiple parallel grooves are recessed from front side surfaces of the multi-grooved interposer in a third direction toward a back side surface of the multi-grooved interposer. The multiple conductive strips continuously extend across recessed surfaces in the multiple parallel grooves and the front side surfaces along the second direction with an undulating surface profile to provide electrically conductive paths across the multiple parallel grooves. Each of the multiple parallel grooves is configured to receive an edge of a respective semiconductor chip.

SEMICONDUCTOR DEVICE

There is provided a semiconductor device 1 which comprises: a housing comprising a first housing electrode 5 and a second housing electrode 4 which are arranged at opposite sides of the housing; a plurality of semiconductor units 30 arranged within the housing between the first and second housing electrodes 4, 5; a plurality of pressure means 40 for applying pressure to the plurality of semiconductor units 30, respectively, wherein the plurality of pressure means 40 are arranged between the plurality of semiconductor units 30 and the first housing electrode 5; a first conductive structure 14 arranged between the plurality of pressure means 40 and the plurality of semiconductor units 30, wherein the plurality of semiconductor units 30 are electrically connected in parallel between the second housing electrode 4 and the first conductive structure 14; and a second conductive structure 18 configured to provide a current flow path from the first conductive structure 14 to the first housing electrode 5, the second conductive structure comprising a first part 16 that is fixedly connected to the first conductive structure 14 and a second part 9 that is fixedly connected to the first housing electrode 5.

Hybrid felts of electrospun nanofibers
10293289 · 2019-05-21 · ·

The present invention relates generally to compositions for use in biological and chemical separations, as well as other applications. More specifically, the present invention relates to hybrid felts fabricated from electrospun nanofibers with high permeance and high capacity. Such hybrid felts utilize derivatized cellulose, and at least one non-cellulose-based polymer that may be removed from the felt by subjecting it to moderately elevated temperatures and/or solvents capable of dissolving the non-cellulose-based polymer to leave behind a porous nanofiber felt having more uniform pore sizes and other enhanced properties when compared to single component nanofiber felts.

Hybrid felts of electrospun nanofibers
10293289 · 2019-05-21 · ·

The present invention relates generally to compositions for use in biological and chemical separations, as well as other applications. More specifically, the present invention relates to hybrid felts fabricated from electrospun nanofibers with high permeance and high capacity. Such hybrid felts utilize derivatized cellulose, and at least one non-cellulose-based polymer that may be removed from the felt by subjecting it to moderately elevated temperatures and/or solvents capable of dissolving the non-cellulose-based polymer to leave behind a porous nanofiber felt having more uniform pore sizes and other enhanced properties when compared to single component nanofiber felts.

SEMICONDUCTOR APPARATUS

According to the present invention, a semiconductor apparatus includes a semiconductor device, a case surrounding the semiconductor device, a spring terminal including a first connection portion extending to a top surface of the case, and a second connection portion provided on the top surface of the case and a control substrate provided on the second connection portion, wherein the first connection portion is connected to the semiconductor device, the second connection portion includes a first end connected to an end of the first connection portion, and a second end opposite to the first end, the second connection portion being a flat plate and having an elastic force using the first end as a supporting point, the second end contacts the control substrate with an elastic force, and the second connection portion has a constriction structure having a notch formed in a side surface along a longitudinal direction.

INTERCONNECTION STRUCTURE FOR INTEGRATED CIRCUIT PACKAGE
20240266278 · 2024-08-08 ·

An interconnection structure for IC package onto the external device is discussed. The IC package has a voltage regulator contained therein; and the external device has a load assembled thereupon. A plurality of connection devices with elasticity are attached to the IC package, so that when a perpendicular force is applied to the connection devices, the IC package is electrically coupled to the external device to provide power supply to the load with ease replacement.

Interposer having a pattern of sites for mounting chiplets

The described embodiments include an interposer with signal routes located therein. The interposer includes a set of sites arranged in a pattern, each site including a set of connection points. Each connection point in each site is coupled to a corresponding one of the signal routes. Integrated circuit chiplets may be mounted on the sites and signal connectors for mounted integrated circuit chiplets may coupled to some or all of the connection points for corresponding sites, thereby coupling the chiplets to corresponding signal routes. The chiplets may then send and receive signals via the connection points and signal routes. In some embodiments, the set of connection points in each of the sites is the same, i.e., has a same physical layout. In other embodiments, the set of connection points for each site is arranged in one of two or more physical layouts.