A duplexer may be used to isolate a transmitter and a receiver that share a common antenna. By using impedance gradients to provide impedances that cause balance-unbalance transformers (balun) of the duplexer to cut-off access to the common antenna rather than duplicate the antenna impedance, the duplexer is balanced. Such cut-offs may have a lower insertion loss than a duplexer that merely duplicates the antenna impedance to separate the differential signals of the receiver and transmitter from the common mode signal.

A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the g.sub.m of the input stage of the amplifier, thus improving the noise figure of the amplifier.

Bias schemes for cascode power amplifiers are disclosed. In certain embodiments, a power amplifier system includes a cascode power amplifier powered by a first supply voltage and that amplifies a radio frequency input signal, and a bias circuit including a voltage regulator that generates a regulated voltage and is powered by the first supply voltage. The bias circuit further includes a bias voltage generation circuit that receives the regulated voltage and generates at least one cascode bias voltage for the cascode power amplifier, a switch that gates a second supply voltage to generate a gated supply voltage, a bias current generation circuit that controls a bias current of the cascode power amplifier and is powered by the gated supply voltage, and a gating circuit that controls the switch based on the regulated voltage and the second supply voltage.

A power amplifier circuit includes a first amplifier transistor, a first nonlinear element, and a current control circuit. The first amplifier transistor has a base or a gate into which a first signal is input, a collector or a drain from which a signal resulting from amplification of the first signal is output, and an emitter or a source that is grounded. The first nonlinear element is connected between the collector or the drain of the first amplifier transistor and the base or the gate of the first amplifier transistor. The current control circuit is connected between the ground and the base or the gate of the first amplifier transistor and controls current flowing through the first nonlinear element.

A power amplifier circuit includes a first transistor having an emitter electrically connected to a common potential, a base to which a first high-frequency signal is input, and a collector from which a third high-frequency signal is output; a second transistor having an emitter electrically connected to the common potential, a base to which a second high-frequency signal is input, and a collector from which a fourth high-frequency signal is output; a first capacitance circuit electrically connected between the collector of the second transistor and the base of the first transistor; and a second capacitance circuit electrically connected between the collector of the first transistor and the base of the second transistor.

A fast-switching average power tracking (APT) power management integrated circuit (PMIC) is provided. The fast-switching APT PMIC includes a voltage amplifier(s) and an offset capacitor(s) having a small capacitance (e.g., between 10 nF and 200 nF). The voltage amplifier(s) is configured to generate an initial APT voltage(s) based on an APT target voltage(s) and the offset capacitor(s) is configured to raise the initial APT voltage(s) by an offset voltage(s) to generate an APT voltage(s). In embodiments disclosed herein, the offset voltage(s) is modulated based on the APT target voltage(s). Given the small capacitance of the offset capacitor(s), it is possible to adapt the offset voltage(s) fast enough to thereby change the APT voltage(s) within a predetermined temporal limit (e.g., 0.5 μs). As a result, the fast-switch APT PMIC can enable a power amplifier(s) to support dynamic power control with improved linearity and efficiency.

An improved method of providing high burst power to audio amplifiers from limited power sources, using parallel power paths to increase system efficiency without need for a power path controller, thus utilizing a simplified circuit operation and maximizing average power available for both the amplifier and supporting circuitry.

Systems, methods, and apparatus for beam steering and switching are disclosed. In one or more examples, a method for operating a communication system comprises switching, at least one switch in a rearrangeable switch network, to control input levels to power amplifiers in a power distribution network. The method further comprises outputting, by the power amplifiers in the power distribution network, power to a plurality of antenna elements. Further, the method comprises steering and distributing power, by the antenna elements, in beams associated with each of the antenna elements according to a level of the power in each of the antenna elements.

Systems, methods, and apparatus for beam steering and switching are disclosed. In one or more examples, a method for operating a communication system comprises switching, at least one switch in a rearrangeable switch network, to control input levels to power amplifiers in a power distribution network. The method further comprises outputting, by the power amplifiers in the power distribution network, power to a plurality of antenna elements. Further, the method comprises steering and distributing power, by the antenna elements, in beams associated with each of the antenna elements according to a level of the power in each of the antenna elements.

Doherty radio frequency (RF) amplifier circuitry includes an input node, an output node, a main amplifier path, and a peaking amplifier path. The main amplifier path is coupled between the input node and the output node and includes a main amplifier. The peaking amplifier path is coupled in parallel with the main amplifier path between the input node and the output node, and includes a peaking amplifier and a peaking variable gain preamplifier between the input node and the peaking amplifier. The peaking variable gain preamplifier is configured to adjust a current provided to the peaking amplifier.