Provided is a high-gain amplifier based on double-gain boosting including a first gain amplification unit including a first amplifier, a second amplifier, and a an interstage matching network connected between the first amplifier and the second amplifier and performing primary amplification; and a second gain amplification unit connected in parallel with the first gain amplification unit and performing secondary boosting.

Provided is a high-gain amplifier based on double-gain boosting including a first gain amplification unit including a first amplifier, a second amplifier, and a an interstage matching network connected between the first amplifier and the second amplifier and performing primary amplification; and a second gain amplification unit connected in parallel with the first gain amplification unit and performing secondary boosting.

In a distributed amplifier, a plurality of cascode amplifiers connected in parallel between an input side transmission line and an output side transmission line are provided, a transmission line is connected to an input terminal of an output transistor of each of the amplifiers, and a bias potential is applied from a bias circuit to the input terminal of the output transistor via the transmission line.

The system response time of a factorized power architecture may be reduced using a high bandwidth accelerator connected in parallel with a low bandwidth switching regulator to feed one or more downstream high bandwidth current multipliers, e.g. at the point of load. The accelerator may use a high speed linear amplifier to drive the factorized bus using stored energy derived from the bus or a low voltage bias supply. The accelerator may alternatively be connected in series between the switching regulator and the downstream current multipliers.

The system response time of a factorized power architecture may be reduced using a high bandwidth accelerator connected in parallel with a low bandwidth switching regulator to feed one or more downstream high bandwidth current multipliers, e.g. at the point of load. The accelerator may use a high speed linear amplifier to drive the factorized bus using stored energy derived from the bus or a low voltage bias supply. The accelerator may alternatively be connected in series between the switching regulator and the downstream current multipliers.

A transmitter merges even and odd data streams to drive a serialized signal. Identical even and odd drivers take turns driving symbols from respective even and odd streams using respective pull-up transistors and pull-down transistors. Each transistor exhibits a significant source-gate capacitance that is charged when the transistor is turned onto drive the serialized signal. Charging one of these capacitances loads the power supply and thus introduces noise. Each even and odd driver includes a pre-driver that times the charging of a source-gate capacitance in the active driver to the discharge of a source-gate capacitance in the inactive driver. The discharge of the source-gate capacitance in the inactive driver counters the effect of charging the active driver, providing much of the power required by the active driver and thus reducing supply noise.

A transmitter merges even and odd data streams to drive a serialized signal. Identical even and odd drivers take turns driving symbols from respective even and odd streams using respective pull-up transistors and pull-down transistors. Each transistor exhibits a significant source-gate capacitance that is charged when the transistor is turned onto drive the serialized signal. Charging one of these capacitances loads the power supply and thus introduces noise. Each even and odd driver includes a pre-driver that times the charging of a source-gate capacitance in the active driver to the discharge of a source-gate capacitance in the inactive driver. The discharge of the source-gate capacitance in the inactive driver counters the effect of charging the active driver, providing much of the power required by the active driver and thus reducing supply noise.

A supply voltage circuit for reducing in-rush battery current in an envelope tracking (ET) integrated circuit (ETIC) is provided. The ETIC includes an ET voltage circuit configured to generate a time-variant ET voltage, which includes an offset voltage, in multiple time intervals based on a supply voltage. In some cases, the offset voltage and the supply voltage may both need to be increased or decreased as the time-variant ET voltage increases or decreases. As the offset voltage and the supply voltage increase or decrease, an excessive in-rush battery current may result in a reduced battery life. In this regard, a supply voltage circuit is configured to help the ETIC to adapt the supply voltage on a per-symbol basis. As a result, it is possible to reduce the in-rush battery current in the ETIC while still allowing the time-variant ET voltage to change in a timely manner.

A supply voltage circuit for reducing in-rush battery current in an envelope tracking (ET) integrated circuit (ETIC) is provided. The ETIC includes an ET voltage circuit configured to generate a time-variant ET voltage, which includes an offset voltage, in multiple time intervals based on a supply voltage. In some cases, the offset voltage and the supply voltage may both need to be increased or decreased as the time-variant ET voltage increases or decreases. As the offset voltage and the supply voltage increase or decrease, an excessive in-rush battery current may result in a reduced battery life. In this regard, a supply voltage circuit is configured to help the ETIC to adapt the supply voltage on a per-symbol basis. As a result, it is possible to reduce the in-rush battery current in the ETIC while still allowing the time-variant ET voltage to change in a timely manner.

A circuit comprises an amplifier network including a first amplifier and a second amplifier and a first transistor having a first base. The first transistor is thermally isolated from the second amplifier. The circuit further comprises a second transistor having a second base. The second transistor is thermally linked to the second amplifier. The circuit further comprises coupling circuitry configured to couple the first base to the second base.