A power stabilization circuit including a first reference power supply, a second reference power supply, and a combiner circuit coupled to the first reference power supply and the second reference power supply. The first reference power supply is configured to receive a first control signal, generate a first reference signal based on the first control signal, and provide the first reference signal to a first output power supply. The second reference power supply is configured to receive a second control signal, generate a second reference signal based on the second control signal, and provide the second reference signal to a second output power supply. The combiner circuit is configured to generate a combined reference signal based on the first reference signal and the second reference signal and drive a reference load based on the combined reference signal.

A power stabilization circuit including a first reference power supply, a second reference power supply, and a combiner circuit coupled to the first reference power supply and the second reference power supply. The first reference power supply is configured to receive a first control signal, generate a first reference signal based on the first control signal, and provide the first reference signal to a first output power supply. The second reference power supply is configured to receive a second control signal, generate a second reference signal based on the second control signal, and provide the second reference signal to a second output power supply. The combiner circuit is configured to generate a combined reference signal based on the first reference signal and the second reference signal and drive a reference load based on the combined reference signal.

In an RFIC provided in a semiconductor device according to an embodiment, a low-noise amplifier (41) for reception and a power amplifier (11) for transmission are connected to a common antenna connection terminal (5). Between the antenna connection terminal (5) and an LNA (41), a circuit (31) is connected to be used for impedance matching, and a semiconductor switch (SW1) is connected in parallel with the circuit (31).

This disclosure provides systems, devices, apparatus and methods, including computer programs encoded on storage media, for a DPD training procedure. A base station may transmit, for a plurality of iterations, a signal to at least one UE through a plurality of transmit chains and with application of DPD. The signal transmitted for each iteration may be transmitted with a BW that extends over a plurality of subcarriers and includes pilots extending over a BW subset that increases in subcarrier size for each iteration. The base station may receive, for each iteration, feedback from the at least one UE based on the transmitted signal and apply DPD to each of the plurality of transmit chains based on the feedback. Accordingly, the base station may transmit to one or more UEs through the plurality of transmit chains and with application of the DPD pilot signals that extend over the entire BW.

An amplifier arrangement comprises N amplifier stages, wherein N is an integer equal or greater than five. The amplifier arrangement comprises a first cascade of quarter wavelength transmission line segments coupled to receive a first set of amplifier stages, and at least a second cascade of quarter wavelength transmission line segments coupled to receive a second set of amplifier stages. The first cascade and second cascade are connected to a common node, for example in parallel to an output node, or in parallel to an intermediate node.

An amplifier arrangement comprises N amplifier stages, wherein N is an integer equal or greater than five. The amplifier arrangement comprises a first cascade of quarter wavelength transmission line segments coupled to receive a first set of amplifier stages, and at least a second cascade of quarter wavelength transmission line segments coupled to receive a second set of amplifier stages. The first cascade and second cascade are connected to a common node, for example in parallel to an output node, or in parallel to an intermediate node.

A circuit arrangement for amplifying radio signals between a terminal device and an antenna and to a corresponding circuit arrangement is disclosed. The circuit arrangement has a transmission amplifier path and a reception amplifier path. A signal power in a first frequency range in the transmitting direction is detected to determine a transmitted signal power and a signal power in a second frequency range in the receiving direction is detected to determine a received signal power. The detected transmitted signal power can be compared with the detected received signal power. If the detected transmitted signal power is stronger than the detected received signal power, the transmission amplifier path can amplify transmitted signals in the first frequency range. If the detected received signal power is stronger than the detected transmitted signal power, the reception amplifier path can amplify received signals in the second frequency range.

A circuit arrangement for amplifying radio signals between a terminal device and an antenna and to a corresponding circuit arrangement is disclosed. The circuit arrangement has a transmission amplifier path and a reception amplifier path. A signal power in a first frequency range in the transmitting direction is detected to determine a transmitted signal power and a signal power in a second frequency range in the receiving direction is detected to determine a received signal power. The detected transmitted signal power can be compared with the detected received signal power. If the detected transmitted signal power is stronger than the detected received signal power, the transmission amplifier path can amplify transmitted signals in the first frequency range. If the detected received signal power is stronger than the detected transmitted signal power, the reception amplifier path can amplify received signals in the second frequency range.

A DPD (1) includes: a polynomial structure including a pseudo-interpolation/sub-sample-shift processing unit (101) configured to operate at a sampling rate for sampling an input signal not upsampled in a previous stage of the DPD (1), pseudo-interpolate a sample point between sample points of the input signal, and shift the pseudo-interpolated sample point by a sub-sample and a multiplexer (109) configured to select a combination of a sub-sample shift amount; and an FIR filter (107) configured to be provided in a subsequent stage of the polynomial structure and include a sub-sample delay filter delaying a sample point of the input signal by a sub-sample. The DPD (1) compensates for distortion due to a sample point of the input signal and compensates for distortion due to a sub-sample point between sample points of the input signal for the DPD (1), by using the polynomial structure and the FIR filter (107).

A method for digital predistortion (DPD) calibration in a wireless communication device is provided that includes transmitting, by transmission circuitry of the wireless communication device, a plurality of pulses, where each pulse corresponds to an amplitude step in a pattern of amplitude steps, where the amplitude steps are separated by silence gaps, receiving each pulse in receiver circuitry of the wireless communication device, generating, by an accumulator component of the wireless communication device, an accumulated sample for each pulse based on a plurality of samples output by the receiver circuitry for the pulse, and computing, by a processor of the wireless communication device, amplitude dependent gain (AM/AM) and amplitude dependent phase shift (AM/PM) values for each accumulated sample.