An RF amplifier comprises a first ‘transconductance’ transistor (N.sub.CS) arranged to receive an RF input voltage (RFIN) at its gate terminal. A second ‘cascode’ transistor (N.sub.CG) has its source terminal connected to the drain terminal of the first transistor (N.sub.CS) at a node (MID). A feedback circuit portion is configured to measure a node voltage at the node (MID), to determine an average of the node voltage, to compare said average node voltage to a predetermined reference voltage (V.sub.BCG), and to generate a control voltage (CGGATE) dependent on the difference between the average node voltage and the predetermined reference voltage (V.sub.BCG). The feedback circuit portion applies the control voltage (CGGATE) to the gate terminal of the second transistor (N.sub.CG).

A semiconductor device including an error amplifier configured to receive a voltage of an output node and a reference voltage, a flipped voltage follower (FVF) circuit configured to receive an output of the error amplifier and maintain the voltage of the output node at the reference voltage, and a bias current control circuit configured to receive first to third mode signals, control a magnitude of a bias current flowing through the FVF circuit based on the first to third mode signals, control the bias current of a first magnitude, based on the first mode signal, control the bias current of a second magnitude smaller than the first magnitude, based on the second mode signal, and control the bias current of a third magnitude smaller than the second magnitude, based on the third mode signal.

An operational amplifier compensation circuit includes; a first transistor activated/deactivated in response to a signal level difference between an input signal applied to an operational amplifier and an output signal provided by the operational amplifier, a first signal amplifying circuit including a second transistor and a first load, wherein the first signal amplifying circuit is configured to generate a first gate voltage amplified in response to the voltage level difference between the input signal and the output signal in relation to an internal resistance of the second transistor and a resistance of the first load when the first transistor is activated, and a third transistor configured to generate a first compensation current in response to the amplified first gate voltage and provide the first compensation current to the operational amplifier.

An electromyography (EMG) device according to an aspect of the present disclosure includes a main circuit board having opposing first and second faces. A plurality of first connectors of a first type are provided on the first face, and a plurality of input contacts are provided on the second face. An EMG circuit is provided on the main circuit board. The EMG circuit is configured to utilize the input contacts as inputs to obtain an EMG input signal, and process the EMG input signal to provide an EMG output signal that is based on, but different from, the EMG input signal. For each of the input contacts, there is no conductive path directly between the input contact and any of the first connectors.

An electromyography (EMG) device according to an aspect of the present disclosure includes a main circuit board having opposing first and second faces. A plurality of first connectors of a first type are provided on the first face, and a plurality of input contacts are provided on the second face. An EMG circuit is provided on the main circuit board. The EMG circuit is configured to utilize the input contacts as inputs to obtain an EMG input signal, and process the EMG input signal to provide an EMG output signal that is based on, but different from, the EMG input signal. For each of the input contacts, there is no conductive path directly between the input contact and any of the first connectors.

An amplifier circuit includes multiple transistors, a set of input routing circuits, and a set of output routing circuits. Each output routing circuit corresponds to an input routing circuit. Each input routing circuit and its corresponding output routing circuit are controlled by one or more control signals. Each input routing circuit is configured to selectively connect each transistor of a transistor pair to a first input terminal of the amplifier circuit, a second input terminal of the amplifier circuit, or a third input terminal of the amplifier based on a value of the one or more control signals. Each output routing circuit is configured to selectively connect each transistor of the transistor pair to a first output terminal of the amplifier circuit, a second output terminal of the amplifier circuit, or a calibration circuit based on the value of the one or more control signals.

A signal receiver includes a data sampler receiving a differential input signal having first and second input signals and determining bit values of the differential input signal based on first and second reference voltages, and a reference voltage generator performing a pre-tuning operation and a post-tuning operation to generate the reference voltages. The reference voltage generator performs the pre-tuning operation by generating first and second initial voltages and adjusting one of the initial voltages to generate third and fourth voltages. After the pre-tuning operation, the reference voltage generator performs the post-tuning operation by increasing or decreasing the third voltage to generate the first reference voltage and decreasing or increasing the fourth voltage to generate the second reference voltage based on a comparison result between the third voltage and the first input signal and a second comparison result between the fourth voltage and second input signal.

A linear power supply circuit includes: an output stage including a first output transistor and a second output transistor, which are provided between an input terminal to which an input voltage is able to be applied and an output terminal to which an output voltage is able to be applied and are connected in parallel to each other; a driver configured to drive the first output transistor and the second output transistor based on a difference between a voltage based on the output voltage and a reference voltage; a resistor inserted between a gate of the first output transistor and a gate of the second output transistor; a capacitor having one end connected to the input terminal and the other end connected to a connection node between the resistor and the gate of the second output transistor; and a clamp element connected in parallel to the resistor.

A device includes an analog main signal path and a digital control circuit. The digital control circuit determines and provides a digital control signal to the analog main signal path to reduce a gain error of the analog main signal path.

A signal processing circuit. In some embodiments, the signal processing circuit includes a first sample and hold circuit and a second sample and hold circuit. The first sample and hold circuit may include: a hold capacitor; an input switch connected between a common input node and the hold capacitor; a signal path amplifier having an input connected to the hold capacitor; and an output switch connected between an output of the signal path amplifier and a common output node. An input of a voltage feedback amplifier may be connected to the hold capacitor, and an output of the voltage feedback amplifier may be operatively coupled to an internal node of the input switch.