A temperature detection circuit (1) includes a first transistor (Q1) of a bipolar type, and a second transistor (Q2) of a bipolar type, wherein the first transistor (Q1) and the second transistor (Q2) form a current mirror circuit (10), and the temperature of the amplifier circuit (30) is detected based on a temperature change of the first transistor (Q1) and the second transistor (Q2).

A bias circuit for a RF amplifier is described. The bias circuit includes a first transistor and a second transistor configured as a first current mirror. A first current source is arranged between a supply node and the first transistor first terminal. An output of the bias circuit is coupled to the second transistor second terminal. A second current mirror coupled to the first current mirror and the bias circuit output. The bias circuit includes a first resistor coupled between a first transistor control terminal and a second transistor control terminal and a variable capacitor coupled between the second transistor control terminal and a ground.

A bias circuit includes a first transistor and a second transistor configured as a first current mirror. A first current source is arranged between a supply node and the first transistor first terminal. A bias circuit output is coupled to the second transistor second terminal. A second current mirror is coupled to the first current mirror and the bias circuit output. A second current source is arranged between the supply node and the second current mirror. A third transistor in a diode-connected configuration is coupled between the first transistor second terminal and a ground. Alternatively or in addition, the bias circuit includes a first variable capacitor coupled between the second transistor first terminal and the second transistor second terminal. A fourth transistor has a control terminal coupled to the supply node, a first terminal coupled to the supply node and a second terminal coupled to the second transistor first terminal.

A signal envelope detector is provided. The signal envelope detector includes an input node configured to receive an input signal. Further, the signal envelope detector includes a capacitive voltage divider coupled to the input node and configured to generate an attenuated input signal by voltage division of the input signal. The signal envelope detector additionally includes a source follower transistor coupled between a first node configured to receive a first voltage supply signal and a second node configured to receive a second voltage supply signal. A gate terminal of the source follower transistor is coupled to the capacitive voltage divider and configured to receive the attenuated input signal. The signal envelope detector includes a rectifier circuit configured to receive and rectify an output signal of the source follower transistor. In addition, the signal envelope detector includes a low-pass filter coupled to the rectifier circuit and configured to generate an envelope signal indicative of a rectified envelope of the input signal by low-pass filtering of an output signal of the rectifier circuit.

A semiconductor integrated circuit includes a first pad provided on one end side of a first resistive element and one end side of a second resistive element externally provided, a second pad provided on a different end side of the first resistive element, a third pad provided on a different end side of the second resistive element and one end side of a third resistive element externally provided, an operation amplifier, a first signal line, wired between an output terminal of the operation amplifier and the first pad, a second signal line wired between an inverting input terminal of the operation amplifier and the second pad, a third signal line wired between the inverting input terminal of the operational amplifier and the third pad, a first ESD protection element, provided to the first signal line, a fourth signal line, through which a voltage signal of the first pad.

A semiconductor integrated circuit includes a first pad provided on one end side of a first resistive element and one end side of a second resistive element externally provided, a second pad provided on a different end side of the first resistive element, a third pad provided on a different end side of the second resistive element and one end side of a third resistive element externally provided, an operation amplifier, a first signal line, wired between an output terminal of the operation amplifier and the first pad, a second signal line wired between an inverting input terminal of the operation amplifier and the second pad, a third signal line wired between the inverting input terminal of the operational amplifier and the third pad, a first ESD protection element, provided to the first signal line, a fourth signal line, through which a voltage signal of the first pad.

A circuit may include amplifier circuitry configured to receive a current signal at an amplifier input node, convert the current signal to a voltage signal, and output the voltage signal at an amplifier output node. The circuit may also include overload circuitry configured to receive a replica DC input voltage and a replica DC output voltage. The overload circuitry may be further configured to detect that the current signal exceeds a threshold level based on the replica DC input voltage and the replica DC output voltage. In addition, the overload circuitry may be configured to, in response to and based on detecting that the current signal exceeds the threshold level, direct DC current of the current signal through a DC shunt path and direct AC current of the current signal through an AC shunt path. The AC shunt path may be different from the DC shunt path.

Power amplifier bias circuit. A power amplifier bias circuit can include an emitter follower device and an emitter follower mirror device coupled to form a mirror configuration. The emitter follower device can be configured to provide a bias signal for a power amplifier at an output port. The power amplifier bias circuit can include a reference device configured to mirror an amplifying device of the power amplifier. The emitter follower mirror device can be configured to provide a mirror bias signal to the reference device.

Power amplifier bias circuit. A power amplifier bias circuit can include an emitter follower device and an emitter follower mirror device coupled to form a mirror configuration. The emitter follower device can be configured to provide a bias signal for a power amplifier at an output port. The power amplifier bias circuit can include a reference device configured to mirror an amplifying device of the power amplifier. The emitter follower mirror device can be configured to provide a mirror bias signal to the reference device.

In one aspect, a buffer circuit comprises a source or emitter follower input stage and output stage. A load is provided between the stages which comprises a representation of an output load of the buffer circuit. This improves the circuit linearity whilst enabling a high input impedance to be obtained. In another aspect, a buffer circuit comprises a source or emitter follower output stage. A load is in the form of a filter is provided and which comprises a representation of an output load of the buffer circuit.