Certain aspects of the present disclosure generally relate to a low voltage, accurate current mirror, which may be used for distributed sensing of a remote current in an integrated circuit (IC). One example current mirror typically includes a first pair of transistors, a second pair of transistors in cascode with the first pair of transistors, a switching network coupled to the second pair of transistors, and a third pair of transistors coupled to the switching network. An input node between the first and second pairs of transistors may be configured to receive an input current for the current mirror, and an output node at the first pair of transistors may be configured to sink an output current for the current mirror, proportional to the input current. This current mirror architecture offers a hybrid low-voltage/high-voltage solution, tolerates low input voltages, provides high output impedance, and offers low area and power consumption.

A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.

A bidirectional amplifier includes first and second ports, with a first summing node connected to the first port and a second summing node connected to the second port. First and second gain stages are connected between the first and second summing nodes, respectively, and a first node. First and second feedback stages are also connected between the first and second summing nodes, respectively, and the first node. The amplifier operates in a first mode in which an amplified version of a signal applied to the first port is provided at the second port, or a second mode in which an amplified version of a signal applied to the second port is provided at the first port. The first and second gain stages are preferably first and second common emitter cascode arrangements, and the first and second feedback stages are preferably first and second emitter followers.

An integrated circuit and method are provided. The integrated circuit comprises: a digital core configured to output a first voltage signal: and a first input/output cell: wherein the first input/output cell is configured to convert the first voltage signal to a first current signal and provide the first current signal to circuitry external to the integrated circuit.

An integrated circuit and method are provided. The integrated circuit comprises: a digital core configured to output a first voltage signal: and a first input/output cell: wherein the first input/output cell is configured to convert the first voltage signal to a first current signal and provide the first current signal to circuitry external to the integrated circuit.

An apparatus for performing capacitor amplification in an electronic device may include a first resistor and a second resistor that are connected in series and coupled between a set of input terminals of a receiver in the electronic device, a common mode capacitor having a first terminal coupled to a common mode terminal and having a second terminal, and an alternating current (AC)-coupled amplifier that is coupled between the common mode terminal and the second terminal of the common mode capacitor. The first resistor and the second resistor may be arranged for obtaining a common mode voltage at the common mode terminal between the first resistor and the second resistor. In addition, the common mode capacitor may be arranged for reducing a common mode return loss. Additionally, the AC-coupled amplifier may be arranged for performing capacitor amplification for the common mode capacitor.

Telescopic amplifier circuits are disclosed. In an embodiment, a telescopic amplifier includes an input stage for receiving differential input signals, an output stage for outputting differential output signals at the drains of a first output transistor and a second output transistor, a tail current transistor coupled to sources of a first input transistor and a second input transistor, a common mode feedback circuit coupled to the differential output signals and outputting a common mode output signal, and a circuit element coupled between the common mode output signal and a gate of the tail current transistor. In an embodiment the circuit element is a resistor. In another embodiment the circuit element is a source follower transistor. In additional embodiments a phase margin of the common mode feedback open loop gain of the amplifier is determined by the value of the resistor. Additional embodiments are disclosed.

This application relates to amplifier circuitry for amplifying a signal from a MEMS transducer. A super source follower circuit (40) is provided which includes a feedback path from its output node (N.sub.out) to a control bias node (BC) in order to provide a preamplifier signal gain that may be greater than unity. A first transistor (M1) is configured to have its gate node connected to an input node (N.sub.IN) for receiving the input signal (V.sub.IN) and its drain node connected to an input node (X) of an output stage (A). The source node of the first transistor is connected to the output node (N.sub.OUT). A current source (I2) is configured to deliver a current to the drain node of the first transistor (M1), wherein the current source (I2) is controlled by a bias control voltage (V.sub.BC) at the bias control node (BC). A feedback impedance network (Z1) comprising a first port connected to the output node (N.sub.OUT) and a second port connected to the bias control node (BC) is provided.

Methods and circuits for maximizing gain of a voltage follower circuit are provided. The method includes using a NMOS voltage replica generation circuit, a PMOS voltage replica generation circuit, a NPN BJT voltage replica generation circuit, a n-channel JFET voltage replica generation circuit, a P-Channel JFET voltage replica generation circuit and a PNP BJT voltage replica generation circuit. The overall gain for the various transistor families is almost equal to unity.

Methods and circuits for maximizing gain of a voltage follower circuit are provided. The method includes using a NMOS voltage replica generation circuit, a PMOS voltage replica generation circuit, a NPN BJT voltage replica generation circuit, a n-channel JFET voltage replica generation circuit, a P-Channel JFET voltage replica generation circuit and a PNP BJT voltage replica generation circuit. The overall gain for the various transistor families is almost equal to unity.