Disclosed is a capacitive sensor chip based on a power-aware dynamic charge-domain amplifier array. The capacitive sensor chip is based on a zoom architecture and includes: an architecture having two or more stages for capacitive quantization in which a first stage performs coarse quantization using a successive approximation register (SAR) and a second stage performs fine quantization using a delta-sigma modulator, an amplifier in the capacitive sensor chip is powered by a floating capacitor, the floating capacitor is connected to a power supply to being charged and connected to the amplifier to power the amplifier by controlling switches; a first-order integrator of the delta-sigma modulator includes an amplifier array having a scale of N bits and 2.sup.N amplifiers where N is a positive integer. By the capacitive sensor chip based on the power-aware dynamic charge-domain amplifier array, utilization efficiency of charges can be effectively improved, power consumption overheads nay be effectively saved, energy efficiency of a system is greatly improved and a driving capability of the subsequent-stage amplifier may be adaptively distributed according to the size of an input capacitance.

Disclosed is a capacitive sensor chip based on a power-aware dynamic charge-domain amplifier array. The capacitive sensor chip is based on a zoom architecture and includes: an architecture having two or more stages for capacitive quantization in which a first stage performs coarse quantization using a successive approximation register (SAR) and a second stage performs fine quantization using a delta-sigma modulator, an amplifier in the capacitive sensor chip is powered by a floating capacitor, the floating capacitor is connected to a power supply to being charged and connected to the amplifier to power the amplifier by controlling switches; a first-order integrator of the delta-sigma modulator includes an amplifier array having a scale of N bits and 2.sup.N amplifiers where N is a positive integer. By the capacitive sensor chip based on the power-aware dynamic charge-domain amplifier array, utilization efficiency of charges can be effectively improved, power consumption overheads nay be effectively saved, energy efficiency of a system is greatly improved and a driving capability of the subsequent-stage amplifier may be adaptively distributed according to the size of an input capacitance.

A circuit arrangement is provided which includes an array of stages for photon counting current to voltage conversion. Each stage includes a tunable operational transconductance amplifier and a feedback network forming a feedback loop of the operational transconductance amplifier. Each stage is configured to provide an output signal as a function of an input signal that is provided to the amplifier input of the operational transconductance amplifier, wherein the input signal comprises one or more current pulses and the output signal comprises one or more voltage pulses. With the tunable operational transconductance amplifier the transconductance of a stage can be tuned so that differences in peaking time and gain are avoided. Furthermore, an imaging device and a method for operating a circuit arrangement are provided.

A shaper circuit includes a first amplifier including an input and an output, the input being configured to receive an input signal, which includes one or more current pulses, a feedback component coupled to the output and to the input of the first amplifier thereby forming a feedback loop of the first amplifier, and an RC component coupled to the output of the first amplifier and to a reference potential terminal. Therein the shaper circuit is configured to provide an output signal as a function of the input signal, the output signal including one or more voltage pulses, and the RC component is configured to largely cancel a low frequency pole of the feedback loop of the first amplifier.

Disclosed preamplifier circuit comprises amplifier arranged in first current path between input node and output node of the preamplifier circuit. Feedback capacitor is arranged in second current path between said input and output nodes. Feedback circuit having adjustable transfer function is arranged in third current path between said input and output nodes. Reset switch arranged in said third current path enables selectively coupling output of the feedback circuit to input of the amplifier and decoupling output of the feedback circuit from input of the amplifier. Loop controller is arranged selectively, in dependence of voltage in the preamplifier circuit, one of open reset switch to set preamplifier circuit in normal operating mode and close reset switch to set preamplifier circuit in reset mode. Loop controller is arranged to adjust the transfer function of the feedback circuit at least in part in dependence of the current operating mode of the preamplifier circuit.

Disclosed preamplifier circuit comprises amplifier arranged in first current path between input node and output node of the preamplifier circuit. Feedback capacitor is arranged in second current path between said input and output nodes. Feedback circuit having adjustable transfer function is arranged in third current path between said input and output nodes. Reset switch arranged in said third current path enables selectively coupling output of the feedback circuit to input of the amplifier and decoupling output of the feedback circuit from input of the amplifier. Loop controller is arranged selectively, in dependence of voltage in the preamplifier circuit, one of open reset switch to set preamplifier circuit in normal operating mode and close reset switch to set preamplifier circuit in reset mode. Loop controller is arranged to adjust the transfer function of the feedback circuit at least in part in dependence of the current operating mode of the preamplifier circuit.

An oscillator includes a resonator, sustaining circuit and detector circuit. The sustaining circuit receives a sense signal indicative of mechanically resonant motion of the resonator generates an amplified output signal in response. The detector circuit asserts, at a predetermined phase of the amplified output signal, one or more control signals that enable an offset-reducing operation with respect to the sustaining amplifier circuit.

An oscillator includes a resonator, sustaining circuit and detector circuit. The sustaining circuit receives a sense signal indicative of mechanically resonant motion of the resonator generates an amplified output signal in response. The detector circuit asserts, at a predetermined phase of the amplified output signal, one or more control signals that enable an offset-reducing operation with respect to the sustaining amplifier circuit.

A circuit for startup of a multi-stage amplifier circuit includes a pair of input nodes and at least two output nodes configured to be coupled to a multi-stage amplifier circuit. A startup differential stage includes a differential pair of transistors having respective control terminals coupled to the pair of input nodes, and each transistor in the differential pair of transistors has a respective current path therethrough between a respective output node and a common source terminal. The startup differential stage is configured to sense a common mode voltage drop at a first differential stage of the multi-stage amplifier circuit. Current mirror circuitry includes a plurality of transistors coupled to the common terminal of the differential pair of transistors and coupled to two output nodes of the at least two output nodes.

Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.