An average power tracking (APT) power management integrated circuit (PMIC) is provided. The APT PMIC is configured to generate an APT voltage to a power amplifier for amplifying a high modulation bandwidth (e.g., ≥200 MHz) radio frequency (RF) signal. The APT PMIC includes a voltage amplifier configured to generate an initial APT voltage and an offset capacitor configured to raise the initial APT voltage by a modulated offset voltage. The APT PMIC can be configured to modulate the initial APT voltage and the modulated offset voltage concurrently based on a time-variant APT target voltage. As a result, the APT PMIC can adapt the APT voltage very quickly between different voltage levels, thus making it possible to amplify a high modulation bandwidth radio frequency (RF) signal for transmission in a fifth-generation (5G) communication system.

An inverted group delay circuit is provided. The inverted group delay circuit can offset a group delay between a pair of signals. In a non-limiting example, the inverted group delay circuit can be configured to offset a group delay (e.g., negative group delay) between a time-variant voltage and a time-variant envelope of an analog signal. More specifically, the inverted group delay circuit can output an inverted time-variant voltage having an opposing phase and time-adjusted relative to the time-variant voltage to thereby offset the group delay between the time-variant voltage and the time-variant envelope. As such, the inverted group delay circuit can be provided in a power management integrated circuit (PMIC) to improve timing alignment between a time-variant voltage(s) and a time-variant analog signal(s) at a power amplifier(s), thus helping to reduce potential amplitude distortion when the analog signal(s) is amplified by the power amplifier(s).

In some embodiments, an amplifier system can include an amplifier circuit having first and second amplifiers configured to amplify respective first and second portions of an input signal. Each of the first and second amplifiers can include a cascode stage with input and output transistors arranged in a cascode configuration. The amplifier system can further include an envelope tracking bias circuit coupled to the amplifier circuit and configured to provide a bias signal to the output transistor of the cascode stage of at least one of the first and second amplifiers. The amplifier system can further include a supply circuit configured to provide a non-envelope tracking supply voltage to the output transistor of the cascode stage of the at least one of the first and second amplifiers.

A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.

An envelope tracking (ET) amplifier apparatus is provided. The ET amplifier apparatus includes a distributed ET integrated circuit (DETIC) configured to generate a distributed ET voltage. The DETIC may be coupled to a higher-bandwidth (HB) amplifier circuit and a lower-bandwidth (LB) amplifier circuit configured to amplify an HB radio frequency (RF) signal and an LB RF signal, respectively. In examples discussed herein, the DETIC may be configured to selectively provide the ET voltage to one of the HB amplifier circuit and the LB amplifier circuit, depending on which of the HB amplifier circuit and the LB amplifier circuit is activated. By providing the DETIC in proximity to the HB amplifier circuit and the LB amplifier circuit, it may be possible to reduce potential distortion to the HB RF signal and the LB RF signal, without significantly increasing footprint of the ET amplifier apparatus.

A wide bandwidth power amplifier apparatus is provided. The wide bandwidth power amplifier apparatus includes a power amplifier circuit, a primary switcher circuit, a voltage circuit(s), and an auxiliary switcher circuit(s). The power amplifier circuit is configured to amplify a radio frequency (RF) signal based on a modulated voltage and a modulated current. The voltage circuit is configured to generate the modulated voltage and a respective part of the modulated current. The primary switcher circuit and the auxiliary switcher circuit are each configured to also generate a respective part of the modulated current. The auxiliary switcher circuit only generates the respective part of the modulated current when a bandwidth of the modulated voltage exceeds a bandwidth threshold. As such, it is possible to prevent the voltage circuit from having to source additional current when the modulated voltage exceeds the bandwidth threshold, thus helping to improve efficiency of the voltage circuit.

A transmitter apparatus that performs beamforming with phase correction uses power detectors present between power amplifiers (PAs) and antennas are used to measure power amplitudes on at least two transmission paths. The sum and difference of these amplitudes are then evaluated to determine a phase difference therebetween. A phase of one signal contributing to the sum and difference may be modified until the sum and difference are the same. Based on an amount of phase modification, a correction signal may be sent to a beamforming circuit to provide phase correction during beamforming.

A power amplifier system is disclosed with a carrier amplifier having a carrier bias input and a carrier supply node and a peaking amplifier having a peaking bias input and a peaking supply node. Also included is an envelope tracking power supply having a modulated voltage supply output coupled to the peaking supply node. Further included is a peaking bias controller having a peaking bias control input coupled to the peaking supply node and a peaking bias control output coupled to the peaking bias input, wherein the peaking bias controller is configured to generate in response to a modulated peaking supply voltage generated by the envelope tracking power supply at the peaking supply node a modulated peaking bias signal that controls bias of the peaking amplifier.

One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.

Envelope tracking systems for power amplifiers are provided herein. In certain embodiments, an envelope tracker is provided for a power amplifier that amplifies an RF signal. The envelope tracker includes a multi-level switching circuit having an output that provides an output current that changes in relation to an envelope signal indicating an envelope of the RF signal when the envelope tracker is operating in an envelope tracking mode. The multi-level switching circuit includes a multi-level supply (MLS) modulator that receives multiple regulated voltages of different voltage levels, and an MLS control circuit that controls the selection of the MLS modulator over time based on the envelope signal. When transitioning the MLS modulator from selection of one regulated voltage level to another regulated voltage level, the MLS control circuit provides a soft transition to gradually switch the regulated voltage levels.