Patent classifications
H03F2200/18
ADAPTIVE BIAS CIRCUITS AND METHODS FOR CMOS MILLIMETER-WAVE POWER AMPLIFIERS
Adaptive bias networks include small transistors connected to adjust gate bias voltage of one or more transistors of an amplifier or amplifier stage, or in a main or auxiliary path of a compound amplifier such as a Doherty amplifier. The small transistors are sized to avoid additional loading of the input. The adaptive bias circuits of preferred embodiments adjust the gate bias to produce a boost in gate bias voltage of an nFET transistor when the input power is in an upper portion of the amplifier or amplifier stage's input power range, thereby increasing the gain, and reduce gate bias voltage of a pFET transistor in the upper portion of the amplifier's input power range, thereby also increasing the gain. The adaptive bias networks can be implemented with varactors to vary DC voltage across the varactor to change its capacitance and compensate changing input capacitance of the amplifier input FET.
POWER AMPLIFIER CIRCUIT
A power amplifier circuit includes: a transistor which is supplied at a base with a bias current, amplifies an input signal, and outputs a current; a transistor which is connected at a base to the base of the transistor and in which a current commensurate with the current is input to a collector; a transistor which outputs a bias control signal which controls supply of the bias current; and a control circuit which is connected to the collector of the transistor and a gate of the transistor and controls a bias control signal on the basis of a reference current based on a reference signal and the current.
Apparatus for optimized turn-off of a cascode amplifier
An apparatus for turning off a cascode amplifier having a common-base transistor and a common-emitter transistor is disclosed that includes the cascode amplifier, a feedback circuit, and a bias circuit. The feedback circuit is configured to receive a collector-voltage from the collector of the common-emitter transistor when the common-emitter transistor is switched to a first OFF state and produce a first feedback signal. The collector-voltage is equal to an emitter voltage of the common-base transistor and the collector-voltage increases in response to switching the common-emitter transistor to the first OFF state. The bias circuit is configured to receive the first feedback signal and produce a bias-voltage. A first base-voltage is produced from the bias-voltage. The cascode amplifier is configured to receive the first base-voltage and a second base-voltage. The common-base transistor is configured to switch to a second OFF state in response to receiving the second base-voltage.
Dynamic biasing circuit
A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.
SYSTEM AND METHOD FOR ADJUSTING AMPLIFIER BIAS CURRENT BASED ON INPUT SIGNAL ENVELOPE TRACKING
A system and method which includes receiving an input signal having an envelope and generating an envelope detection signal corresponding to the envelope. A bias current provided to an amplifier circuit is adjusted based upon the envelope detection signal, the amplifier circuit including an amplifier and a transformer. The transformer is configured to establish a magnetically coupled feedback loop from an output of the amplifier to an input of the amplifier. An output signal is provided, by the amplifier circuit, in response to the input signal.
DC coupled amplifier having pre-driver and bias control
A dc coupled amplifier includes a pre-driver, and amplifier and a bias control circuit. The pre-driver is configured to receive one or more input signals and amplify the one or more input signals to create one or more pre-amplified signals. The amplifier has cascode configured transistors configured to receive and amplify the one or more pre-amplified signals to create one or more amplified signals, the amplifier further having an output driver termination element. The bias control circuit is connected between the pre-driver and the amplifier, the bias control circuit receiving at least one bias current from the output driver termination element of the amplifier, wherein the pre-driver, the amplifier and the bias control circuit are all formed on a same die.
RF AMPLIFIER WITH A CASCODE DEVICE
An RF amplifier comprises a first ‘transconductance’ transistor (N.sub.CS) arranged to receive an RF input voltage (RFIN) at its gate terminal. A second ‘cascode’ transistor (N.sub.CG) has its source terminal connected to the drain terminal of the first transistor (N.sub.CS) at a node (MID). A feedback circuit portion is configured to measure a node voltage at the node (MID), to determine an average of the node voltage, to compare said average node voltage to a predetermined reference voltage (V.sub.BCG), and to generate a control voltage (CGGATE) dependent on the difference between the average node voltage and the predetermined reference voltage (V.sub.BCG). The feedback circuit portion applies the control voltage (CGGATE) to the gate terminal of the second transistor (N.sub.CG).
Amplifier
Provided is an amplifier that includes a first transistor including a gate terminal to which an applied input signal is input, where a current depending on the applied input signal flows through the first transistor. A gate terminal of a second transistor is connected to a load section, and a current depending on a change in a voltage of the drain terminal of the first transistor flows through the second transistor. A source terminal of the first transistor and a drain terminal of the second transistor are connected in common to a first resistance, and the current from the first transistor and the current from the second transistor flow through the first resistance. A third transistor supplies a current approximately equal to the current of the second transistor. The current supplied by the third transistor is output from an output end.
Electronic device and wireless communication system thereof
An electronic device includes a network monitor configured to acquire network environment information related to a radio frequency (RF) transmission signal; a transceiver configured to generate an envelope signal of the RF transmission signal; a transmission (Tx) module including a power amplifier for receiving the RF transmission signal from the transceiver and amplifying the RF transmission signal; and an envelope tracking (ET) modulator configured to receive the envelope signal from the transceiver and to provide a bias of a power amplifier to correspond to the envelope signal, wherein the ET modulator determines a magnitude of the bias of the power amplifier based on the network environment information acquired by the network monitor.
Current control circuit and power amplifier circuit
A current control circuit controls a base current of a first transistor included in a bias circuit outputting a bias current to a power amplifier based on a base-collector voltage of the first transistor. The current control circuit includes a first circuit that outputs a signal associated with the base-collector voltage of the first transistor, and a second circuit that, based on the signal, provides electrical continuity between a base of the first transistor and a reference potential.