A bias circuit includes first to fourth transistors and a phase compensation circuit. In the first transistor, a reference current or voltage is supplied to a first terminal, and the first terminal and a second terminal are connected. In the second transistor, a first terminal is connected to the first transistor, and a third terminal is grounded. In the third transistor, a power supply voltage is supplied to a first terminal, a second terminal is connected to the first transistor, and a bias current or voltage is supplied from a third terminal to an amplifier transistor. In the fourth transistor, a first terminal is connected to the third transistor, a second terminal is connected to the second transistor, and a third terminal is grounded. The phase compensation circuit is provided in a path extending from the fourth transistor to the third transistor through the second and first transistors.

An apparatus for turning off a cascode amplifier having a common-gate transistor and a common-source transistor is disclosed that includes the cascode amplifier, a feedback circuit, and a bias circuit. The feedback circuit is configured to receive a drain-voltage from the drain of the common-source transistor when the common-source transistor is switched to a first OFF state and produce a first feedback signal. The drain-voltage is equal to a source voltage of the common-gate transistor and the drain-voltage increases in response to switching the common-source transistor to the first OFF state. The bias circuit is configured to receive the first feedback signal and produce a bias-voltage. A first gate-voltage is produced from the bias-voltage. The cascode amplifier is configured to receive the first gate-voltage and a second gate-voltage. The common-gate transistor is configured to switch to a second OFF state in response to receiving the second gate-voltage.

A dc coupled amplifier includes a pre-driver, and amplifier and a bias control circuit. The pre-driver is configured to receive one or more input signals and amplify the one or more input signals to create one or more pre-amplified signals. The amplifier has cascode configured transistors configured to receive and amplify the one or more pre-amplified signals to create one or more amplified signals, the amplifier further having an output driver termination element. The bias control circuit is connected between the pre-driver and the amplifier, the bias control circuit receiving at least one bias current from the output driver termination element of the amplifier, wherein the pre-driver, the amplifier and the bias control circuit are all formed on a same die.

The present invention discloses a bias compensation circuit. The bias compensation circuit includes a detecting circuit, including a diode-connected transistor circuit, with a first end for receiving a first current, and a second end coupled to a first reference voltage end; and a first diode circuit, with a first end for receiving a second current, and a second end coupled to the first reference voltage end; wherein the detecting circuit provides a first voltage level according to the diode-connected transistor circuit, and provides a second voltage level according to the first diode circuit; a voltage-current converting circuit, coupled to the detecting circuit, for generating a first reference current according to the first voltage level and the second voltage level; and a bias circuit, coupled to the voltage-current converting circuit, for receiving the first reference current, to provide a bias voltage level according to the first reference current.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

According to one aspect, an integrated circuit includes a power amplifier having a succession of at least two amplifier stages. The two amplifier stages include a first amplifier stage configured to receive a radio frequency signal as input and a last amplifier stage configured to deliver as an output of an amplified radio frequency signal. The power amplifier further includes a safety circuit with a control circuit configured to compare the amplified radio frequency signal voltage with a threshold voltage. The safety circuit further comprises a gain reduction circuit configured to reduce a bias voltage of an upstream amplifier stage of the last amplifier stage when the amplified radio frequency signal voltage is greater than the threshold voltage.

An electronic device includes a network monitor configured to acquire network environment information related to a radio frequency (RF) transmission signal; a transceiver configured to generate an envelope signal of the RF transmission signal; a transmission (Tx) module including a power amplifier for receiving the RF transmission signal from the transceiver and amplifying the RF transmission signal; and an envelope tracking (ET) modulator configured to receive the envelope signal from the transceiver and to provide a bias of a power amplifier to correspond to the envelope signal, wherein the ET modulator determines a magnitude of the bias of the power amplifier based on the network environment information acquired by the network monitor.

A biasing circuit with high current drive capability for fast settling of a biasing voltage to a stacked cascode amplifier is presented. According to a first aspect, the biasing circuit uses transistors matched with transistors of the cascode amplifier to generate a boost current during a transition phase that changes the biasing voltage by charging or discharging a capacitor. The boost current is activated during the transition phase and deactivated when a steady-state condition is reached. According to a second aspect, the biasing circuit uses an operational amplifier in a feedback loop that forces a source node of a cascode transistor of a reference circuit, that is a scaled down replica version of the cascode amplifier, to be at a reference voltage. The high gain and high current capability of the operational amplifier, provided by isolating a high frequency signal processed by the cascode amplifier from the reference circuit, allow for a quick settling of the biasing voltage.

A current to digital converter circuit has an integrator amplifier with an input adapted to receive a current signal and an output adapted to provide a voltage signal as a function of an integration of the current signal, a quantizer circuit with an input which is coupled to the output of the integrator amplifier and with an output adapted to provide a binary result signal as a function of a comparison of the voltage signal with at least a first reference voltage signal, a digital-to-analog converter circuit which is coupled in a switchable manner as a function of the binary result signal to the input of the integrator amplifier, and a controlled current source which is coupled to the output of the integrator amplifier via a first switch which is controlled as a function of the binary result signal such that an auxiliary current is supplied to the output of the integrator amplifier.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.