A radio frequency module includes: a module board that includes a first principal surface and a second principal surface on opposite sides of the module board; a power amplifier; and a first circuit component. The power amplifier includes: a first amplifying circuit element; a second amplifying circuit element; and an output transformer that includes a primary coil and a secondary coil. An end of the primary coil is connected to an output terminal of the first amplifying circuit element. Another end of the primary coil is connected to an output terminal of the second amplifying circuit element. An end of the secondary coil is connected to an output terminal of the power amplifier. The first amplifying circuit element and the second amplifying circuit element are disposed on the first principal surface. The first circuit component is disposed on the second principal surface.

An amplifier is formed in a wiring layer. A semiconductor device includes a second layer over a first layer with a metal oxide therebetween. The first layer includes a first transistor including a first semiconductor layer containing silicon. The second layer includes an impedance matching circuit, and the impedance matching circuit includes a second transistor including a second semiconductor layer containing gallium. The first transistor forms first coupling capacitance between the first transistor and the metal oxide, and the impedance matching circuit forms second coupling capacitance between the impedance matching circuit and the metal oxide. The impedance matching circuit is electrically connected to the metal oxide through the second coupling capacitance. The metal oxide inhibits the influence of first radiation noise emitted from the impedance matching circuit on the operation of the first transistor.

A radio-frequency module includes a module substrate, a power amplifier, and a control circuit configured to control the power amplifier. The control circuit includes a temperature sensor. The power amplifier and the control circuit are stacked one on top of another on a principal surface of the module substrate.

A transceiver interface for a phased array element includes a first magnetic circuit having a primary coil and a secondary coil, a second magnetic circuit having a primary coil, a secondary coil and a tertiary coil, a main amplifier path and an auxiliary amplifier path, the main amplifier path coupled to the primary coil of the second magnetic circuit and configured to receive a quadrature signal, the main amplifier path configured to provide a quadrature output signal, the auxiliary amplifier path coupled to the primary coil of the first magnetic circuit and configured to receive an in-phase signal, the auxiliary amplifier path configured to provide an in-phase output signal, a selectable output circuit configured to selectively combine the in-phase output signal and the quadrature output signal, and a low noise amplifier (LNA) coupled to the tertiary coil of the second magnetic circuit.

A circuit for downlink/uplink operational mode switching in a TDD wireless communication system comprises a field-effect transistor operatively connected to a power amplifier on the downlink path of a RF front-end apparatus in a TDD wireless communication system, a first voltage generator connected to a large-value first resistor, a second voltage generator connected to a second resistor, a large-value hold capacitor, and a sample-and-hold circuit configured to be switched between a reception configuration, wherein the first voltage generator is connected to the gate of the field-effect transistor and the large-value capacitor is connected to the first voltage generator through the first resistor, and a transmission configuration, wherein the gate of the field-effect transistor is connected to the hold capacitor and the hold capacitor is connected to the second voltage generator through the second resistor.

An interface card includes a circuit board, a device mounted on the circuit board, and a PMIC mounted on the circuit board. The PMIC includes a PMIC processor communicatively coupled to a host processor of a host system. The PMIC processor is configured to receive an input voltage signal from a power supply that is external to the interface card. The PMIC processor generates at least one output voltage signal based on the input voltage signal. The at least one output voltage signal is supplied to the device. A power enable signal originating from the host processor is detected. The power enable signal is detected at a GPIO connector of the PMIC. The PMIC processor deactivates generation of the at least one output voltage signal based on the power enable signal.

An output switch includes; a plurality of input terminals and output terminals each of the plurality of input terminals is electrically connected to at least one of the plurality of output terminals; a first low noise amplifier that amplifies a signal of a predetermined frequency band input through an antenna and outputs a first signal to a first input terminal among the plurality of input terminals, and a second low noise amplifier that amplifies a signal of a predetermined frequency band input through an antenna and outputs a second signal to a second input terminal different from the first input terminal among the plurality of input terminals. A filter that attenuates a signal of a frequency band higher than a frequency band of the second signal is electrically connected between the second input terminal and the second low noise amplifier.

In a power amplifying module in which a plurality of differential amplifying circuits is mounted on a substrate, each of the differential amplifying circuits includes a chip device that includes at least two amplifiers, each of the at least two amplifiers amplifying a differential signal, a balun that includes a primary side winding wire and a secondary side winding wire, both ends of the primary side winding wire being connected to an output of the chip device, and a capacitor provided between a power feed point of the primary side winding wire and a reference potential. In at least one of the plurality of the differential amplifying circuits, the distance from one end of the primary side winding wire to the power feed point is different from the distance from the other end of the primary side winding wire to the power feed point.

Methods and devices to support multiple gain states in amplifiers are described. The methods and devices are based on implementing a feedback element in the amplifier and adjusting the impedance of the feedback element to provide a desired gain while maintaining the overall performance of the amplifier and reducing degradation of the S12 parameter. The feedback element includes an adjustable attenuator and a tunable resistive element. The adjustable attenuator is provided in a path that is common to the feedback path and the bypass path of the amplifier. Exemplary implementations of adjustable attenuators are also presented.

A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.