A pixel circuit includes a differential amplifier. The differential amplifier includes a non-inverting input terminal, an inverting input terminal, and an output terminal. The differential amplifier includes an input differential pair including first and second NMOS transistors, a current mirror pair including PMOS transistors, and a constant current source including a fifth NMOS transistor. A threshold voltage of each of the first and second NMOS transistors is higher than a threshold voltage of the fifth NMOS transistor. Further, the threshold voltage of each of the first and second NMOS transistors is higher than a threshold voltage of another NMOS transistor.

Amplifier systems for driving a wide range of loads are provided herein. In certain embodiments, an amplifier system includes a voltage output amplifier and a current output amplifier that are electrically coupled in parallel with one another between an input terminal and an output terminal. The amplifier system further includes a control circuit operable to control whether or not the voltage output amplifier and/or current output amplifier drive the output terminal.

Aspects of this disclosure relate to an amplification circuit that includes a stacked amplifier and a bias circuit. The stacked amplifier includes at least a first transistor and a second transistor in series with each other. The stacked amplifier is operable in at least a first mode and a second mode. The bias circuit is configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode. In certain embodiments, the amplification circuit can be a power amplifier stage configured to receive a supply voltage that has a different voltage level in the first mode than in the second mode.

An audio processing circuit includes a cascade operational amplifier circuit, an output node, and a pull-down circuit. The cascade operational amplifier circuit includes a first operational amplifier circuit and a second operational amplifier circuit. The first operational amplifier circuit includes a main operational amplifier and a secondary operational amplifier that are connected in parallel. The pull-down circuit is configured to pull down a voltage at the output node after the first operational amplifier circuit is turned on. The second operational amplifier circuit is configured to, after the secondary operational amplifier is turned on, control a voltage gain of the secondary operational amplifier to change gradually from low to high.

Amplifier systems for driving a wide range of loads are provided herein. In certain embodiments, an amplifier system includes a voltage output amplifier and a current output amplifier that are electrically coupled in parallel with one another between an input terminal and an output terminal. The amplifier system further includes a control circuit operable to control whether or not the voltage output amplifier and/or current output amplifier drive the output terminal.

A preamplifier circuit includes a first transconductor and a floating transconductor. The first transconductor receives a differential voltage from a sample-and-hold circuit and drives the floating transconductor. The first and floating transconductors output amplified versions of the differential voltage that are not affected by capacitive division, which makes the preamplifier circuit fast. The preamplifier circuit also has a low input capacitance because the floating transconductor is not connected to any external circuitry.

A circuit module (100) includes an electronic component (30), a plurality of conductor posts (40), a mold layer (50) that seals a plurality of the electronic components (30) and the plurality of conductor posts (40), and a shield layer (60) on the mold layer (50). The electronic components (30) include a first electronic component (31) and second electronic components (32, 36). The plurality of conductor posts (40) includes a group of conductor posts (400) traversing between the first electronic component (31) and the second electronic components (32, 36). The shield layer (60) includes a slit (600) that, with respect to each conductor post (40) included in the group (400) of conductor posts, in a plan view, passes and extends between the conductor post (40) and the first electronic component (31), or between the conductor post (40) and the second electronic components (32, 36).

Aspects of this disclosure relate to a band pass filter that includes LC resonant circuits coupled to each other by a capacitor. A bridge capacitor can be in parallel with series capacitors, in which the series capacitors include the capacitor coupled between the LC resonant circuits. The bridge capacitor can create a transmission zero at a frequency below the passband of the band pass filter. The LC resonant circuits can each include a surface mount capacitor and a conductive trace of the substrate, and an integrated passive device die can include the capacitor. Band pass filters disclosed herein can be relatively compact, provide relatively good out-of-band rejection, and relatively low loss.

In an embodiment an integration circuit has a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, an output terminal to provide an output signal as a function of the first and the second input signal, a first and a second amplifier, each being switchably connected between the first or the second input terminal and the output terminal, and a capacitor which is switchably coupled in a feedback loop either of the first or of the second amplifier such that the capacitor and one of the first and the second amplifier form an inverting integrator providing the output signal. Therein the integration circuit is prepared to be operated in a first and a second subphase, wherein in each of first and second subphases one of the first and the second input signals is supplied to the inverting integrator and the respective other one of first and the second input signals is supplied to the respective other one of the first and the second amplifier.

A dynamic amplifier with a bypass design. An input pair of transistors receives a pair of differential inputs Vip and Vin and further provides first, second and third terminals. A load circuit provides a pair of differential outputs Vop and Von with the load circuit connected at a common mode terminal. In an amplification phase, a driver for amplification is coupled to the first terminal and the load circuit is coupled to the second and third terminals. A bypassing circuit is specifically provided. The bypassing circuit is coupled to the second and third terminals during a bypass period within the amplification phase.