A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.

The invention discloses a dual-mode power amplifier with switchable working power and a mode switch method. The power amplifier adopts a multi-tap input transformer, and realizes the switching between preload line and output load line by controlling the on/off of the intermediate switch connected with taps, so as to achieve the best power conversion efficiency under different maximum output powers. By using the change-over switch to control the capacitance value of the matching capacitor, it is easier to adjust the load line, thus further ensuring the performance of the power amplifier provided by the invention. The intermediate switch and change-over switch are integrated on an independent chip by CMOS/phemt/bihemt/SeGe/SOI, etc, or on a power amplifier chip by CMOS/phemt/bihemt/SeGe/SOI, etc, which is easy to realize.

A power amplifier includes a semiconductor die, and an amplifier and bias circuit integrally formed with the semiconductor die. The die has opposed first and second sides, and a device bisection line extends between the first and second sides. The bias circuit includes a multi-point input terminal with first and second terminals that are electrically connected through a conductive path that extends across the device bisection line, and one or more bias circuit components connected between the multi-point input terminal and the amplifier. The amplifier may include a field effect transistor (FET) with gate and drain terminals, and the bias circuit component(s) are electrically connected between the multi-point input terminal and the gate terminal. In addition or alternatively, the bias circuit component(s) are electrically connected between a multi-point input terminal and the drain terminal. The one or more components may include a resistor-divider circuit.

This application provides a variable gain amplifier and a phased array transceiver, to enable the variable gain amplifier to keep a phase constant when switching a gain, and to enable a gain step to be stable with a frequency. The variable gain amplifier includes an amplification circuit, configured to amplify an input signal; a control circuit, configured to control a gain of the amplification circuit by adjusting an output current of the amplification circuit; and an inductive load and an inductive adjustment circuit, where the inductive load is coupled to a signal output end of the amplification circuit, the inductive adjustment circuit and the inductive load are inductively coupled, and the inductive adjustment circuit is adjustable.

A high-frequency module (1) includes a mounting substrate (90), a duplexer (60L) arranged on the mounting substrate (90), a duplexer (60H) arranged on the mounting substrate (90) and having a pass band with a higher frequency than a pass band of the duplexer (60L), and a semiconductor control IC (40) arranged on the mounting substrate (90) and stacked with the duplexer (60L) of the duplexers (60L and 60H).

A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.

Apparatus and methods for biasing power amplifiers are provided herein. In certain embodiments, a power amplifier includes a bipolar transistor having a base biased by a bias network having a reactance that controls an impedance at the transistor base to achieve substantially flat phase response over large dynamic power levels. For example, the bias network can have a frequency response, such as a high-pass or band-pass response, that reduces the impact of power level on phase distortion (AM/PM).

A power amplifier module includes an amplifier transistor and a bias circuit. A first power supply voltage based on a first operation mode or a second power supply voltage based on a second operation mode is supplied to the amplifier transistor. The amplifier transistor receives a first signal and outputs a second signal obtained by amplifying the first signal. The bias circuit supplies a bias current to the amplifier transistor. The bias circuit includes first and second resistors and first and second transistors. The first transistor is connected in series with the first resistor and is turned ON by a first bias control voltage which is supplied when the first operation mode is used. The second transistor is connected in series with the second resistor and is turned ON by a second bias control voltage which is supplied when the second operation mode is used.

An electrically conductive sub-collector layer is provided in a surface layer portion of a substrate. A collector layer, a base layer, and an emitter layer are located within the sub-collector layer when viewed in plan. The collector layer is connected to the sub-collector layer. An emitter electrode and a base electrode are long in a first direction when viewed in plan. The emitter electrode overlaps the emitter layer. The base electrode and the emitter electrode are discretely located away from each other in a second direction orthogonal to the first direction. A collector electrode is located on one side in the second direction with respect to the emitter electrode and is not located on the other side when viewed in plan. A base line is connected to the base electrode in a manner so as to adjoin a portion other than longitudinal ends of the base electrode.

A communication circuit and an electronic device comprising the communication circuit are provided. The communication circuit includes an amplifier module including a first amplifier and a second amplifier for amplifying a signal amplified by the first amplifier, and a first matching circuit that is disposed outside the amplifier module and performs impedance matching between the first amplifier and the second amplifier, wherein the amplifier module includes a first terminal for outputting, to the outside, the signal amplified by the first amplifier, and a second terminal for a signal that is input to the second amplifier, and the first matching circuit may be connected to the amplifier module via the first terminal and the second terminal.