An integrated circuit includes a first high-pass filter having an input coupled to receive a first signal and an output coupled to a first input of a first differential pair of transistors. A second high-pass filter includes an input coupled to receive a second signal and an output coupled to a second input of the first differential pair of transistors. The second signal may be a complementary signal of the first signal. A second differential pair of transistors includes control electrodes coupled to a first voltage supply terminal. A boost circuit is coupled between the second differential pair of transistors and the first voltage supply terminal. A low-pass filter is coupled between the first differential pair of transistors and the second differential pair of transistors.

Features and advantages of the present disclosure include a multimode voltage controlled oscillator (VCO). In one embodiment, a circuit comprises a VCO, first and second transistors, and first and second capacitive attenuators. The first and second transistors are cross coupled through the attenuators. In a first mode, the first and second transistors are turned off, and the capacitive attenuators attenuate a signal on output terminals of the VCO at control inputs of the first and second transistors. In another mode, the first and second transistors are turned on, and the capacitive attenuation is reduced or turned off so that control inputs of the first and second transistors receive signals on the outputs of the VCO.

A power amplifier circuit includes a transistor having a first terminal that is configured to receive an input signal, a second terminal electrically coupled to ground, and a third terminal configured to transmit a combined amplified signal. The power amplifier circuit further includes a combining signal input path electrically coupled to the second terminal and configured to receive a combining signal and provide the combining signal to the second terminal of the transistor to generate, at least in part, the combined amplified signal.

An amplifier circuits inductive/magnetic sensor interface can include a main signal path including one or more amplifiers configured to receive an input signal and to produce an output signal based on the input signal. The input signal may include a square-wave demodulated signal having an associated modulation frequency and an undesired frequency component at twice the modulation frequency of the square-wave demodulated signal. The amplifier circuit may include a gain feedback loop configured to set a gain of the amplifier circuit. The amplifier circuit may include a ripple reduction feedback loop configured to receive an intermediate signal on the main signal path and extract the undesired frequency component of the intermediate signal to produce a filtered version of the intermediate signal and provide the filtered version of the intermediate signal to the main signal path.

A radar system includes a transmitter circuit, which transmits a radar wave having a chirp frequency gradually increasing or decreasing to a target, and a frequency conversion circuit, which demodulates a signal of the radar wave reflected at the target by frequency-conversion in correspondence to the chirp frequency. A radar signal processor includes a variable amplifier connected to an output side of the frequency conversion circuit, and a feedback circuit which detects an output of the variable amplifier as a detection signal and feeds back a signal of a frequency band included in the detection signal to an input of the variable amplifier. The feedback circuit is configured to cut off and not cut off a frequency band including a DC offset transient response frequency, which occurs at time of frequency conversion by the frequency conversion circuit, during a specified period and a period other than the specified period, respectively. The specified period is a predetermined first period from starting of a demodulation operation of the frequency conversion circuit and/or a predetermined second period from ending of the demodulation operation of the frequency operation of the frequency conversion circuit.

A class D amplifier includes a self-oscillating class D amplification circuit that is driven by an output current signal; and a voltage-current converting circuit that outputs an output current signal in response to an input signal voltage and an output signal voltage from a feedback signal voltage.

Systems and methods of noise suppression by an amplifier are presented. In one exemplary embodiment, an amplifier comprises first and fourth transistors configured as a first differential pair of transistors in a common-gate configuration, and second and third transistors configured as a second differential pair of transistors in a common-source configuration. The first and fourth transistors are operative to receive, from a differential input, by a source of each first and fourth transistor, a differential input signal. Further, a drain of each first and fourth transistor is coupled to respective first and second outputs configured as a differential output. The second and third transistors are operative to output, from a drain of each second and third transistor, to the respective second and first outputs, a differential output signal. Further, a gate of each second and third transistor is coupled to the respective first and second inputs.

An apparatus includes an amplifier, an input port, a first modulator circuit connected to the input port, and a correction circuit. The correction circuit is configured to determine a common mode voltage of the input port and receive a first clock signal. The correction circuit is further configured to manipulate, based at least in part upon the common mode voltage of the input port, the first clock signal to generate a second clock signal. The second clock signal is produced for the first modulator circuit. The correction circuit is further configured to determine whether the second clock signal is out of phase with a third clock signal, and, based upon a determination that the second clock signal is out of phase with the third clock signal, reset the second clock signal.

A radar sensor includes a mixer configured to receive an radio frequency (RF) input signal to down-convert the RF input signal into a base-band or intermediate frequency (IF) band, an analog-to-digital converter (ADC), and a signal processing chain coupled between the mixer and the ADC. The radar sensor further includes an oscillator circuit that is configured to generate a test signal. The ADC is coupled to an output of the signal processing chain, and is configured to generate a digital signal by digitizing an output signal of the signal processing chain, the output signal being derived from the test signal. The radar sensor further includes a digital signal processing circuit coupled to the ADC downstream thereof, the digital signal processing circuit being configured to perform a spectral analysis on frequency values of the digital signal.

A compound semiconductor device includes: a first layer of nitride semiconductor, the first layer being doped with Fe; a channel layer of nitride semiconductor above the first layer; and a barrier layer of nitride semiconductor above the channel layer, wherein the channel layer includes: a two-dimensional electron gas region in which the two-dimensional electron gas exists; and an Al-containing region between the two-dimensional electron gas region and the first layer, an Al concentration in the Al-containing region being 510.sup.17 atoms/cm.sup.3 or more and less than 110.sup.19 atoms/cm.sup.3.