A multi-bit digital signal that is generated by modulating a baseband signal by a modulation circuit and includes components in a radio frequency band is amplified by switch-mode amplifiers (100-1, 100-2) on a bit-by-bit basis, amplified signals are band-limited by frequency-variable variable band limiting units (201-1, 201-2) and thereafter subjected to voltage-to-current conversion by voltage/current source conversion units (202-1, 202-2) provided with variable capacitances, the signals converted to current are synthesized at a synthesis point X, and a resultant signal is impedance-corrected by an impedance correction unit (203) and output as a transmission signal to an antenna of a load (300). Consequently, the present invention provides a transmitter capable of synthesizing output signals from a plurality of switch-mode amplifiers and transmitting a resultant signal while maintaining an impedance characteristic with respect to a plurality of transmit frequencies without increasing a circuit size.

A tunable matching circuit for use with ultra-low power RF receivers is described to support a variety of RF communication bands. A switched-capacitor array and a switched-resistor array are used to adjust the input impedance presented by the operating characteristics of transistors in an ultra-low-power mode. An RF sensor may be used to monitor performance of the tunable matching circuit and thereby determine optimal setting of the digital control word that drives the switched-capacitor array and switched-resistor array. An effective match over a significant bandwidth is achievable. The optimal matching configuration may be updated at any time to adjust to changing operating conditions. Memory may be used to store the optimal matching configurations of the switched capacitor array and switched resistor array.

Aspects of this disclosure relate to an amplification circuit that includes a stacked amplifier and a bias circuit. The stacked amplifier includes at least a first transistor and a second transistor in series with each other. The stacked amplifier is operable in at least a first mode and a second mode. The bias circuit is configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode. In certain embodiments, the amplification circuit can be a power amplifier stage configured to receive a supply voltage that has a different voltage level in the first mode than in the second mode.

A delay-compensating power management circuit is provided. The power management circuit includes a power management integrated circuit (PMIC) configured to generate a time-variant voltage(s) based on a time-variant target voltage(s) for amplifying an analog signal(s) associated with a time-variant power envelope(s). A voltage processing circuit is provided in the power management circuit to determine a temporal offset, which can be positive or negative, between the time-variant power envelope(s) and the time-variant target voltage(s). Accordingly, the voltage processing circuit modifies the time-variant target voltage(s) to substantially reduce the determined temporal offset and thereby realign the time-variant target voltage(s) with the time-variant power envelope(s). By realigning the time variant target voltage(s) with the time-variant power envelope(s), it is possible to align the time-variant voltage(s) with the time-variant power envelope(s) to reduce distortions (e.g., amplitude clipping) during amplification of the analog signal.

A transmitter according to the present invention includes: a baseband amplitude value distribution processor (90) for changing a distribution of an amplitude value of a baseband signal based on a control signal that has been input and outputting the baseband signal as an output signal; a digital transmitter (91) that ΔΣ modulates the output signal and transmits the modulated signal; an in-band distortion measurement unit (92) for measuring an in-band distortion amount of the output signal; an amplitude value distribution measurement unit (93) for calculating an amplitude value distribution of the output signal; a sideband distortion prediction unit (94) for predicting a sideband distortion amount occurring in the output signal by the digital transmitter (91) from the calculated amplitude value distribution; and a baseband processing controller (95) for adjusting the control signal based on the measured in-band distortion amount and the sideband distortion amount and outputting the adjusted signal.

A novel and useful linear, efficient, smart wideband CMOS hybrid power amplifier that combined an analog linear amplification path and a digital power amplification (DPA) path. PA path control logic analyzes the input I and Q signals and determines which amplification paths to steer the input I and Q signals to. The analog linear amplification path comprises digital to analog converters for both I and Q paths and one or more analog linear power amplifiers. The digital power amplification path comprises I and Q up-sampling circuits and I and Q RF DAC circuits (e.g., digital PA circuits). In operation, the PA path control logic compares the I and Q signals to thresholds (which may or may not be different) and based on the comparisons, selects one or more paths for the input I and Q signals. Whether the signals from the analog and digital amplification paths are to be combined or selected (i.e. switched), the PA path control circuit is operative to generate select (switch) control signals which are applied to summer/selector elements which generate the output of the hybrid PA.

Apparatus and methods for bias switching of power amplifiers are provided herein. In certain configurations, a power amplifier system includes a power amplifier that provides amplification to a radio frequency (RF) signal and a bias control circuit that biases the power amplifier. The power amplifier includes an amplification transistor that receives the RF signal at an input, and a first bias network and a second bias network each connected to the input. The bias control circuit includes a first switch, a first reference current source that provides the first reference current to the first bias network through the first switch, a second switch, and a second reference current source that provides the second reference current to the second bias network through the second switch.

A phase shift circuitry includes: a signal generation circuitry that receives an input signal, and outputs four signals different in phase from each other by 90 degrees based on the input signal, the four signals includes a first signal and a second signal; four variable amplifier circuitry that each includes a transistor, and amplify the four signals individually, with amplification factors based on control voltages supplied to gates of the transistors, the four variable amplifier circuitry include a first amplifier amplifies the first signal by a first control voltage and a second amplifier amplifies the second signal by a second control voltage; a synthetic circuitry that synthesizes output signals of the four variable amplifier circuitry, and outputs a synthesized signal; and a control circuitry supplies voltages, that are equal to or higher than the gate threshold value, to the first amplifier and the second amplifier.

An outphasing amplifier having: a first branch to receive and process a first branch signal, the first branch signal being phase modulated, with constant amplitude envelope; and a second branch arranged to receive and process a second branch signal, the second branch signal being phase modulated, with constant amplitude envelope, and at least a portion of the second branch signal anti-phase from the first branch signal, wherein each branch includes: circuitry arranged to process the signal to reduce the energy in sidebands of the signal away from the central frequency, while retaining the phase information in the signal; and an amplifier arranged to amplify the filtered and re-asserted branch signal.

A low-noise amplifier device includes an inductive input element, an amplifier circuit, an inductive output element and an inductive degeneration element. The amplifier device is formed in and on a semiconductor substrate. The semiconductor substrate supports metallization levels of a back end of line structure. The metal lines of the inductive input element, inductive output element and inductive degeneration element are formed within one or more of the metallization levels. The inductive input element has a spiral shape and the an amplifier circuit, an inductive output element and an inductive degeneration element are located within the spiral shape.