Patent classifications
H03F2200/36
Power amplifier and gain reduction circuit thereof
A power amplifier gain attenuation circuit includes: a gain attenuation (reduction) circuit configured to receive an input signal, an external drive signal and a bias voltage, and output a secondary input signal after attenuating the input signal depending on the drive signal and bias voltage; an amplifier including: a bias input terminal configured to receive a bias voltage; a signal input terminal configured to receive a secondary input signal, and an output terminal configured to output a gained output signal. The power amplifier gain attenuation circuit can reduce a gain effectively, and the amount of phase jump caused by the attenuation is quite small.
Multi-mode multi-frequency power amplifier
A multi-mode multi-band power amplifier includes a controller, a wide-band amplifier channel and a fundamental impedance transformer. The controller receives an external signal and outputs a control signal according to the external signal. The wide-band amplifier channel receives single-band or multi-band RF signals through the input terminal, performs power amplification on the RF signals and outputs the RF signals through the output terminal. The fundamental impedance transformer includes a first segment shared by RF signals in all bands, second segments respectively special for RF signals in all bands, and a switching circuit controlled by the controller to separate RF signals subject to power amplification to the second segment in a switchable manner for multiplexed outputs.
Complementary current reusing preamp for operational amplifier
An apparatus includes a preamplifier stage to receive a power supply voltage and generate an output based upon an input. In particular, the preamplifier stage includes a biasing device coupled between the output and a ground node to bias a DC voltage level of the output independently of the power supply voltage. The preamplifier stage also includes a complementary circuit to receive the input and generate the output. The complementary circuit reuses a current through the preamplifier stage to provide an increased transconductance of the preamplifier stage for a given current level.
Transimpedance amplifier with bandwidth extender
A transimpedance amplifier that includes an input configured to receive a current input from an upstream device and output configured to present an output voltage. The current input may be from a photodetector or any other device that is part of an optical signal receiving unit front end. In one configuration, there are three amplifier stages in the transimpedance amplifier connected in series. A feedback path with feedback resistor connects between the input and output of the transimpedance amplifier. A bandwidth extender circuit connects between a stage output and a stage input of the transimpedance amplifier. In a three stage embodiment, the bandwidth extender circuit extends between an input of the second stage and the output of the second stage. The bandwidth extender includes at least one active device configured to provide positive feedback to increase gain. The bandwidth extender circuit is able to be automatically or selectively deactivated to filter unwanted frequency components.
Integrated 3-way Doherty amplifier
A die is described comprising at least one 3-way Doherty amplifier comprising a main stage, a first peak stage and a second peak stage. An input is connected to an input network which is connected to the main stage, first peak stage and second peak stage. The input network includes a first impedance connected to an input of the first peak stage and providing a 90 phase shift and a second impedance connected to an input of the second peak stage and providing a 90 phase shift. An output is connected to an output network which is connected to the main stage, first peak stage and second peak stage. The output network includes a third impedance connected to the output of the first peak stage and providing a 180 phase shift and a fourth impedance connected to the output of the main stage and providing a 90 phase shift.
MULTI-STAGE TRANSIMPEDANCE AMPLIFIER WITH RESISTOR-CAPACITOR (RC) COMPENSATION
A multi-stage transimpedance amplifier comprises a first gain stage cascaded with a second gain stage, the second gain stage's output connected to the first gain stage's inverting input and to the second gain stage's inverting input, a compensation network electrically connected between the first gain stage's output and the second gain stage's output, the first gain stage, the second gain stage, and the compensation network together implementing a transfer function having complex conjugate poles and a real-valued zero, the compensation network comprising a resistor electrically connected in series with a capacitor, the resistance of the resistor and the capacitance of the capacitor determining the positioning of the complex conjugate poles, and a third gain stage cascaded with the second gain stage for introducing an additional pole in the transfer function, the third gain stage's output connected to the second gain stage's non-inverting input.
Power Amplifier and Gain Reduction Circuit Thereof
A power amplifier gain attenuation circuit includes: a gain attenuation (reduction) circuit configured to receive an input signal, an external drive signal and a bias voltage, and output a secondary input signal after attenuating the input signal depending on the drive signal and bias voltage; an amplifier including: a bias input terminal configured to receive a bias voltage; a signal input terminal configured to receive a secondary input signal, and an output terminal configured to output a gained output signal. The power amplifier gain attenuation circuit can reduce a gain effectively, and the amount of phase jump caused by the attenuation is quite small.
Power Amplifier Output Power Control Circuit
A power amplifier output power control circuit includes a first operational amplifier with a negative input terminal configured to receive a power control signal; a first PMOS transistor with a grid electrode connected to an output terminal of the first operational amplifier, a source electrode connected to an external power source, and a drain electrode grounded via a voltage dividing network; a power amplifier with a power end connected to the drain electrode of the first PMOS transistor, an input terminal configured to access to a signal to be amplified, and an output terminal configured to amplify the signal; and a current sampling circuit configured to produce sampling current after sampling current across the first PMOS transistor and providing a negative feedback signal for the positive input terminal of the first operational amplifier according to the sampling current such that total output power of the power amplifier keeps unchanged.
Power amplifier output power control circuit
A power amplifier output power control circuit includes a first operational amplifier with a negative input terminal configured to receive a power control signal; a first PMOS transistor with a grid electrode connected to an output terminal of the first operational amplifier, a source electrode connected to an external power source, and a drain electrode grounded via a voltage dividing network; a power amplifier with a power end connected to the drain electrode of the first PMOS transistor, an input terminal configured to access to a signal to be amplified, and an output terminal configured to amplify the signal; and a current sampling circuit configured to produce sampling current after sampling current across the first PMOS transistor and providing a negative feedback signal for the positive input terminal of the first operational amplifier according to the sampling current such that total output power of the power amplifier keeps unchanged.
Broadband power amplifier systems and methods
Disclosed are systems, devices, and methodologies to reduce harmonics in a radio frequency output signal. A power amplifier system comprises a power amplifier and a tunable output matching network electrically connected between the output of the power amplifier and an output of the tunable output matching network. The tunable output matching network reduces second-order harmonics in an amplified radio frequency signal when the power amplifier operates in a low frequency mode. The tunable output matching network includes traps such as a series inductor and a first capacitor in series with a first switch, a second capacitor in series with a second switch, and a third capacitor in series with a third switch, where the traps are tuned to selected harmonic frequencies when the power amplifier operates in the low frequency band of the operating band of frequencies.