Embedded blocking capacitor structures for wideband amplifier circuits are disclosed. A wideband amplifier circuit includes transistors that output radio frequency (RF) signals. An embedded blocking capacitor structure is operably connected between the terminals of the transistors and an RF output. The embedded blocking capacitor structure distributes a bias voltage to the terminals of the transistors and blocks the bias voltage from passing to the RF output. The embedded blocking capacitor structure also propagates an RF signal to an RF output.

A high frequency amplifier circuit includes an input terminal and an output terminal, transmission power amplifiers that amplify a high frequency signal in first and second frequency bands, each of which is a part of a communication band, at equal to or higher than a prescribed amplification factor, respectively, switches that exclusively switch connection between the input terminal, the transmission power amplifier, and the output terminal, and connection between the input terminal, the transmission power amplifier, and the output terminal, and a transmission filter that is connected between the output terminal and the switch and has a communication band as a pass band, the first frequency band including a frequency band other than the second frequency band, the second frequency band including a frequency band other than the first frequency band.

A transimpedance amplifier system (TIA) for stabilizing high gain and high frequency signals while minimizing parasitic capacitance effects on the transimpedance amplifier system. The TIA includes an operational amplifier having a first input terminal, a second input terminal, and an output terminal. The TIA also includes a signal generating device operatively connected with the first input terminal of the operational amplifier. The TIA also includes a T-network feedback architecture operatively connected with the operational amplifier at the first input terminal of the operational amplifier and the output terminal of the operational amplifier. The T-network feedback architecture has a first impedance network and a second impedance network. The T-network feedback architecture is configured to suppress parasitic capacitance from the transimpedance amplifier system.

An amplifying circuit including a first gain circuit, a second gain circuit, a Miller capacitor, a positive feedback circuit and a feedforward gain circuit. The second gain circuit is configured to receive a first gain signal from the first gain circuit and generate a second gain signal. The Miller capacitor, the positive feedback circuit and the feedforward gain circuit are electrically coupled between an input terminal and an output terminal of the second gain circuit. The positive feedback circuit is configured to feedback the signal of the output terminal of the second gain circuit to the input terminal of the second gain circuit. The feedforward gain circuit is configured to amplify the first gain signal to output a third gain signal to the output terminal of the second gain circuit.

A multi-stage amplifier includes a first stage comprising a first common-source amplifier, a first inductive load network comprising a serial connection of a first load resistor and a first load inductor, and a first source network configured to receive a first signal and output a first load signal, and a first inter-stage inductor configured to couple the first load signal to a second signal; and a second stage comprising a second common-source amplifier, a second inductive load network comprising a serial connection of a second load resistor and a second load inductor, and a second source network configured to receive the second signal and output a second load signal, and a second inter-stage inductor configured to couple the second load signal to a third signal, wherein the first load inductor and the second load inductor are laid out to enhance an inter-stage inductive coupling.

A circuit arrangement is provided which includes an array of stages for photon counting current to voltage conversion. Each stage includes a tunable operational transconductance amplifier and a feedback network forming a feedback loop of the operational transconductance amplifier. Each stage is configured to provide an output signal as a function of an input signal that is provided to the amplifier input of the operational transconductance amplifier, wherein the input signal comprises one or more current pulses and the output signal comprises one or more voltage pulses. With the tunable operational transconductance amplifier the transconductance of a stage can be tuned so that differences in peaking time and gain are avoided. Furthermore, an imaging device and a method for operating a circuit arrangement are provided.

A shaper circuit includes a first amplifier including an input and an output, the input being configured to receive an input signal, which includes one or more current pulses, a feedback component coupled to the output and to the input of the first amplifier thereby forming a feedback loop of the first amplifier, and an RC component coupled to the output of the first amplifier and to a reference potential terminal. Therein the shaper circuit is configured to provide an output signal as a function of the input signal, the output signal including one or more voltage pulses, and the RC component is configured to largely cancel a low frequency pole of the feedback loop of the first amplifier.

A wideband radio-frequency transceiver front-end is provided. The transceiver front-end includes an antenna port and a transmission path coupled to the antenna port comprising a power amplifier and a first matching network. The transceiver front-end further includes a reception path coupled to the antenna port comprising a low noise amplifier and a second matching network. Furthermore, the transceiver front-end includes an impedance inverter coupled in-between the antenna port and the second matching network. Moreover, the transceiver front-end includes a controller comprising switching arrangement for a gate and a drain of the power amplifier. In this context, the controller is configured to initiate a first reception mode by connecting the gate of the power amplifier to ground and by connecting the drain of the power amplifier to a supply voltage.

A TX/RX switch includes a power amplifier (PA), a Low Noise Amplifier (LNA), and an antenna connection. The PA is connected to a PA matching network that has a PA network impedance and a common PA-LNA impedance connected in one or more series-parallel combinations in different embodiments in a transmitting mode. The LNA is connected to a LNA matching network that has a LNA. network impedance and the same common PA-LNA impedance connected in one or more series-parallel combinations in a receive mode. A mode switch can connect the common PA-LNA impedance in different configurations to enable the transmitting and receiving mode respectively. In some embodiments, the mode switch can short or open circuit the connection of the PA matching circuit or the LNA matching circuit to the antenna. In some embodiments, the mode switch can also turn power on or off to the PA or the LNA when the switch is in a mode where the respective amplifier is not selected. Accordingly, with specific design limitations on the common PA-LNA impedance combined with different mode switch configurations of the TX/RX switch components in either the TX or RX mode, the TX/RX switch operates within a design bandwidth without, transmission lines embedded in the TX/RX switch circuitry and provides optimum power transfer from/to the antenna at the antenna connection with reduced noise.

A wideband RF choke circuit includes an input, first and second nodes, and a splitting means coupled between the input, first node, and second node. A first all-pass filter and a first line AC blocker are coupled between the input and the splitting means. Second and third all-pass filters, and second and third line AC blockers, are coupled between the splitting means and the first and second nodes, respectively. A first RF choke has a first end, coupled to the first all-pass filter, and a second end. A second RF choke has a first end, coupled to the second end of the first RF choke, and a second end coupled to the second all-pass filter. A third RF choke has a first end, coupled to the second end of the first RF choke, and a second end coupled to the third all-pass filter.