A circuit configured to amplify a signal from which an offset is cancelled includes an amplifier including an input stage configured to receive an input signal, the amplifier configured to amplify the input signal and output the amplified signal, and a switch including a transistor configured to reset the amplifier in response to a reset signal, the transistor including a body node connecting the transistor to the circuit, the transistor being configured to form a current path between the body node of the transistor and the input stage of the amplifier.

A charge amplifier circuit is provided. The charge amplifier circuit is couplable to a transducer that generates an electrical charge that varies with an external stimulus. The charge amplifier circuit includes an amplification stage having an input node, couplable to the transducer, and an output node. The amplification stage biases the input node at a first direct current (DC) voltage. The charge amplifier circuit includes a feedback circuit, which includes a feedback capacitor, electrically coupled between the input and output nodes of the amplification stage. The feedback circuit includes a resistor electrically coupled to the input node, and a level-shifter circuit, electrically coupled between the resistor and the output node. The level-shifter circuit biases the output node at a second DC voltage and as a function of a difference between the second DC voltage and a reference voltage.

Various techniques are provided to reduce common mode disturbance associated with an amplifier, such as a class D amplifier. In one example, an amplifier includes a power stage configured to generate first and second PWM signals. The amplifier further includes an integration stage comprising input nodes configured to receive an input differential analog signal. The integration stage is configured to generate an output differential analog signal in response to the PWM signals and the input differential analog signal. The amplifier further includes an active compensation circuit configured to provide a compensation signal to the integration stage to reduce disturbances at the input nodes associated with the PWM signals switching between a common mode and a differential mode. Additional devices, systems, and methods are also provided.

A preamplifier amplifies signals input to first and second input terminals. A first switching circuit receives first and second input signals and outputs those to the first and second input terminals. A switched capacitor circuit samples two signals amplified by the preamplifier. Differential signals sampled by the switched capacitor circuit are respectively input to third and fourth input terminals of an integration circuit, and the integration circuit outputs differential signals obtained by those input signals to first and second output terminals. A second switching circuit switches a connection relationship between the switched capacitor circuit and the integration circuit. Each time the cycle changes, the first and second switching circuits switch the connection relationships to cause the signals amplified by the preamplifier to be sampled by double correlation sampling.

An apparatus has four transistors. The first and third transistors each have a gate coupled to a first input terminal and second input terminal respectively, a source coupled to a current source and to a first terminal of a bias voltage source, and a substrate coupled to a second terminal of the bias voltage source. The second and fourth transistors each have a gate coupled to the first input terminal and the second input terminal respectively, a source coupled to the drain of the first and third transistors respectively, a drain coupled to a lower voltage supply and a substrate coupled to its source. The bias voltage source increases the threshold voltages of the first and third transistors above the second and fourth transistors, respectively. This ensures that the first and third transistors turn on after the second and fourth transistors, respectively.

A system for offset cancellation for driving a display panel includes: a plurality of source amplifiers driving the display panel; an image analyzer configured to receive a data input of an image frame and analyze the data input; and a chopping pattern controller connected with the image analyzer and configured to determine a chopping pattern that fits the data input based on analysis results of the image analyzer, and apply the determined chopping pattern to the source amplifiers. The source amplifiers are divided into N groups while the chopping pattern controller is configured to drive source amplifiers in each group by a single chopping control signal. The image analyzer is configured to generate an indicator that indicates whether image data being analyzed corresponds to a general image or one of pre-registered killer pattern images. A method for offset cancellation for driving a display panel is also provided.

An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate.

A sensor offset voltage compensation circuit includes a programmable gain amplifier (PGA) having an input loop configured to receive the signal output by a sensor (e.g., a voltage generated a sensor resistive bridge of a pressure sensor) and an output loop configured to furnish an output signal having a voltage that is greater than the input voltage. An offset compensation voltage is applied to at least one of the input loop or the output loop of the PGA to at least substantially cancel the zero-quantity offset voltage of the sensor from the output voltage.

A receiver for cancelling common mode offset and crosstalk that amplifies a voltage difference between an input signal and a reference voltage to generate first and second output signals and an internal signal, that generates the same third and fourth output signals as the first and second output signals, generates average voltage levels of the third and fourth output signals by using first and second switching elements and low pass filters to output the average voltage levels as first and second feedback signals, and cancels a common mode offset between the first output signal and the second output signal based on a voltage difference between the first feedback signal and the second feedback signal, and that generates a control signal to cancel crosstalk of the internal signal by turning on/off the first and second switching elements connected to the low pass filters.

An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.