A high-frequency signal amplifier circuit is used in a front-end circuit configured to propagate a high-frequency transmission signal and a high-frequency reception signal, and includes an amplifier transistor configured to amplify the high-frequency transmission signal; a bias circuit configured to supply a bias to a signal input end of the amplifier transistor; and a ferrite bead, one end of which is connected to a bias output end of the bias circuit and the other end of which is connected to the signal input end of the amplifier transistor, having characteristics in which impedance in a difference frequency band between the high-frequency transmission signal and the high-frequency reception signal is higher than impedance in DC.

An excessive voltage rise of load voltage, caused by an impedance mismatching on a transmission path, is prevented, and high-frequency power is regenerated. A parallel impedance is connected to the transmission path during the voltage rise, thereby regenerating voltage caused by a standing wave and preventing excessive load voltage, together with enhancing energy usage efficiency. Establishing the parallel impedance for the load impedance, on the transmission path between the high-frequency amplifier circuit of the high-frequency power supply device and the high-frequency load, reduces impedance at the connecting position to prevent generation of excessive voltage on the transmission path, and high-frequency power is regenerated from the transmission path by the parallel impedance.

Embodiments disclosed herein generally relate to power amplifier matching circuits used for matching impedance and harmonic control in a device, such as a cellular phone. In one example, a power amplifier matching circuit includes two DVCs, four inductors, a transistor, and a capacitor. Utilizing the two DVCs, the impedance matching ratio and the center frequency of the circuit are capable of adjustment as needed. Moreover, the inclusion of the two DVCs may also prevent harmonic frequencies from undesirably passing through the power amplifier matching circuit to the antenna of a cellular device. The power amplifier matching circuit may be used in conjunction with an amplifier, where the output of the amplifier is proportional to the current in the circuit.

Integrated filter and electromagnetic coupler assemblies. In certain examples, an integrated filter and electromagnetic coupler assembly includes a filter having a capacitance and a series inductance, the series inductance being connected between an input port and an output port of the integrated filter and electromagnetic coupler assembly, and combination of the capacitance and the series inductance being selected to provide the filter with a passband and a stopband. The integrated filter and electromagnetic coupler assembly further includes a coupling element positioned physically proximate the series inductance and extending between a coupled port and an isolation port of the integrated filter and electromagnetic coupler assembly, the integrated filter and electromagnetic coupler assembly being configured to provide at the coupled port a coupled signal via inductive coupling between the series inductance and the coupling element responsive to receiving an input signal at the input port.

Apparatus and methods for an improved-efficiency Doherty amplifier are described. The Doherty amplifier may include a two-stage peaking amplifier that transitions from an “off” state to an “on” state later and more rapidly than a single-stage peaking amplifier used in a conventional Doherty amplifier. The improved Doherty amplifier may operate at higher gain values than a conventional Doherty amplifier, with no appreciable reduction in signal bandwidth.

In various embodiments, a semiconductor package includes a carrier amplifier connected to a first output of a power divider, and a first output matching network connected to the carrier amplifier and an output combining node. The first output matching network exhibits a phase delay during operation of the carrier amplifier. The semiconductor package includes a phase advance network connected to the first output matching network. The phase advance network is configured to offset at least a portion of the phase delay of the first output matching network. The semiconductor package includes a peaking amplifier connected to a second output of the power divider and the output combining node, and a second output matching network connected to the peaking amplifier.

The present invention relates to an amplifying device and to an amplifying system comprising the same. According to the present invention, an amplifier line-up is presented comprising four amplifying units which is operable in a Doherty mode and an outphasing mode. By integration of Chireix compensating elements in the matching networks used in the amplifying units a bandwidth improvement can be obtained.

A power amplifier comprising an amplifying element for amplifying a signal input to the amplifier, a matching network for varying the reactance presented to the output of the amplifying element at the fundamental frequency of the input signal, the matching network being switchable between first and second operating configurations, wherein in the first operating configuration, a net inductive reactance is presented to the output at the fundamental frequency and in the second operating configuration, a net capacitive reactance is presented to the output at the fundamental frequency.

Cascode amplifier having feedback circuits. In some embodiments, an amplifier can include a first transistor and a second transistor arranged in a cascode configuration, with each transistor having a gate. The amplifier can further include a first feedback circuit implemented between an output of the second transistor and the gate of the second transistor. The amplifier can further include a second feedback circuit implemented between the output of the second transistor and the gate of the first transistor.

A high-performance HBT that is unlikely to decrease the process controllability and to increase the manufacturing cost is implemented. A heterojunction bipolar transistor includes an emitter layer, a base layer, and a collector layer on a GaAs substrate. The emitter layer is formed of InGaP. The base layer is formed of GaAsPBi having a composition that substantially lattice-matches GaAs.