A calculation output unit of a digital amplitude modulation device calculates and outputs a protection index of an amplifier based on a combined output signal or an amplitude modulation signal. A first protection unit outputs to a control unit a first control signal to place an entire amplifier unit in an off-controlled state, based on the protection index. A second protection unit outputs, to the control unit, a second control signal to control an upper limit number of amplifier units that can be on-controlled in parallel and a third control signal to on/off control the upper limit number or less or the initial number of the amplifiers. The control unit on/off controls the power amplifiers based on an input sound signal, the first control signal, the second control signal, and the third control signal.

A power controllable wireless communication device includes a variable gain amplifier having a gain that can be controlled based on a gain control signal, a reference power generation circuit, which generates first reference power and second reference power differing from the first reference power, a sensor circuit supplied with selectively power of a high frequency signal output from the variable gain amplifier, and the first reference power and the second reference power generated by the reference power generation circuit, and a control circuit which generates the gain control signal based on a sensor output from the sensor circuit. When controlling power, the control circuit generates the gain control signal based on ratios among a first sensor output corresponding to the first reference power, a second sensor output corresponding to the second reference power, and a high frequency sensor output corresponding to the power of the high frequency signal.

A circuit includes a final stage that includes an H-bridge comprising first and second half-bridges. A read circuit is configured to read a load current supplied by a class-D audio-amplifier to a load. The read circuit is configured for estimating the load current by reading a current at an output by the first or second half-bridge by measuring a drain-to-source voltage during an ON period of a power transistor of the H-bridge. A sensing circuit is configured to detect a first drain-to-source voltage from a transistor of the first half-bridge and a second drain-to-source voltage from a corresponding transistor of the second half-bridge. The sensing circuit is also configured to compute a difference between the first drain-to-source voltage and the second drain-to-source voltage and to perform an averaging operation on the difference to obtain a sense voltage value to be supplied to an analog-to-digital converter.

The present invention provides a control circuit to stabilize an output power of a power amplifier. The control circuit comprises a voltage clamping loop, a current clamping loop and a loop for reducing power variation under VSWR, where the voltage clamping loop is used to clamp an output voltage of the power amplifier within a defined voltage range, the current clamping loop is used to clamp a current of the power amplifier within a defined current range, and the loop for reducing power variation under VSWR is implemented by an impedance detector to compensate the output power under VSWR variation.

A speaker driver comprising an amplifier, configured to receive a test signal that comprises a plurality of equivalent test-blocks, and provide measurement-signalling for a speaker at the amplifier output. The measurement-signalling comprising a plurality of measurement-blocks, wherein each of the measurement-blocks corresponds to the output of the amplifier for one of the plurality of test-blocks. The speaker driver also includes an output-current-sensor configured to: measure a current level of the measurement-signalling, and provide sensed-signalling that comprises a plurality of sensed-blocks, wherein each of the plurality of sensed-blocks corresponds to one of the plurality of measurement-blocks of the measurement-signalling. The speaker driver further includes a processor configured to either: (a) combine the plurality of sensed-blocks to provide a time-averaged-block; and determine a frequency-spectrum of the time-averaged-block; or (b) determine a frequency-spectrum of each of the plurality of sensed-blocks to provide a plurality of frequency-spectrum-sensed-blocks; and combine the plurality of frequency-spectrum-sensed-blocks to provide a time-averaged-frequency-spectrum-block.

An apparatus for controlling the gain and phase of an input signal input to a power amplifier comprises a gain control loop configured to control the gain of the input signal based on power levels of the input signal and an amplified signal output by the power amplifier, to obtain a predetermined gain of the amplified signal, and a phase control loop configured to obtain an error signal related to a phase difference between a first signal derived from the input and a second signal derived from the amplified signal, and control the phase based on the error signal, to obtain a predetermined phase of the amplified signal. The phase control loop delays the first signal, such that the delayed first signal and the second signal used to obtain the error signal correspond to the same part of the input signal. The apparatus may be included in a satellite.

A radio frequency signal having a constant amplitude is modulated by a digital modulation signal and a radio frequency input signal whose amplitude changes stepwise is generated. The radio frequency input signal is input into a power amplifier that is an evaluation target. A period in which an amplitude of the radio frequency input signal is constant is defined as a measurement period and an output signal of the power amplifier is measured in each of measurement periods in which amplitudes of the radio frequency input signal are different from each other.

An amplifier circuit with improved accuracy is provided that comprises a cascade of amplifier stages, a control line for controlling the amplifier stages, a feedback circuit having an input port for receiving a reference signal, and a feedback loop connecting the feedback circuit to the control line. Via the feedback circuit and the feedback loop, the large signal behavior of the amplifier stage is accurately fixed. As a result, the small signal gain of the amplifier stages has an improved accuracy as well.

A power controllable wireless communication device includes a variable gain amplifier having a gain that can be controlled based on a gain control signal, a reference power generation circuit, which generates first reference power and second reference power differing from the first reference power, a sensor circuit supplied with selectively power of a high frequency signal output from the variable gain amplifier, and the first reference power and the second reference power generated by the reference power generation circuit, and a control circuit which generates the gain control signal based on a sensor output from the sensor circuit. When controlling power, the control circuit generates the gain control signal based on ratios among a first sensor output corresponding to the first reference power, a second sensor output corresponding to the second reference power, and a high frequency sensor output corresponding to the power of the high frequency signal.

Charging and discharging circuits for assisting charge pumps are disclosed. In certain embodiments, a radio frequency (RF) switch system includes an RF switch that receives an RF signal and is controlled by a switch control signal received at an input, a first charge pump configured to generate a first charge pump voltage, a level shifter powered by the first charge pump voltage and that generates the switch control signal based on a switch enable signal, and a charge pump assistance switch coupled to the input of the radio frequency switch and that activates to assist the first charge pump in response to a transition of the switch enable signal from a first state to a second state.